Method for forming raised structures by controlled selective epitaxial growth of facet using spacer

Abstract

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface. The resultant structure can function, for example, as a vertical gate of a DRAM cell, elevated source / drain structures, or other semiconductor device feature.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] The present application is a division of U.S. patent application Ser. No. 10 / 379,494, filed on Mar. 4, 2003, presently pending, which is a division of U.S. patent application Ser. No. 10 / 046,497, filed on Oct. 26, 2001, presently pending, which is a division of U.S. patent application Ser. No. 09 / 816,962, filed Mar. 23, 2001, presently pending.FIELD OF THE INVENTION [0002] The present invention relates to the field of semiconductor device fabrication, and more particularly to vertical transistors and other raised structures of a semiconductor device that are formed by controlled selective epitaxial growth. BACKGROUND OF THE INVENTION [0003] The storage capacity of a memory chip is dependent on the number of memory cells in the chip. High density dynamic random access memory (DRAMs) cells are comprised of two main components, a field-effect transistor (FET) and a storage capacitor. In DRAM fabrication, there is a continuing need to provid...

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Benefits of technology

[0007] The invention utilizes selective epitaxial growth (SEG) to form vertically oriented structures on semiconductor substrates. Crystal growth by SEG along a select facet to form a vertically oriented structure cannot be controlled by varying the growth conditions due to the existence of facets on the crystal having different orientations i.e., (100), (110), (111). However, such control is needed to achieve vertically oriented epitaxial growth and eliminate lateral or horizontal growth that can short circuit closely positioned adjacent devices. The present method employs insulative spacers formed over the sidewalls of the epitaxial layers to eliminate unwanted lateral growth and control the growth of the epitaxial film.

[0020] The invention provides useful and improved vertically oriented structures such as transistor gates and elevated source / drain regions that extend outwardly from a substrate. Such structures are particularly suited for use in a DRAM cell or other semiconductor structure. The vertical nature of the structures allows a larger number of transistors or other semiconductor structures per surface area compared to conventional devices.

Problems solved by technology

However, photolithographic processing limits the minimal size of the feature and the resulting device that can be formed.

Thus, the density of storage cells of a memory array has been limited by the resolution capability of the available photolithographic equipment.

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