Parallel bit interleaver
a bit interleaver and parallel technology, applied in the field of digital communication, can solve the problems of increased latency, impaired parallelism, and limited number of possible bit interleaver configurations
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
embodiment 1
[0109]The following describes the details of a bit interleaver (i.e., a parallel bit interleaver) that satisfies conditions 1 and 2 given above. In the following description, processing and the units performing such processing are labeled with the same reference numbers wherever applicable.
[0110]In the present document, each group of M cyclic blocks and each group of Q constellation words is referred to as a section (or as an interleaver section).
[0111]FIGS. 19 and 20 are block diagrams respectively illustrating the mapping function of a bit interleaver satisfying Conditions 1 and 2 and corresponding to the aforementioned parameters (i.e., Q=8, M=4, N=12), and a sample configuration for such a bit interleaver.
[0112]In FIGS. 19 and 20, the QC-LDPC codewords are made up of N=12 cyclic block, each in turn made up of Q=8 bits. Each of the 24 constellation words is made up of M=4 bits. Each constellation word indicates one of 2M=16 constellation points. The bit interleaver is divided int...
embodiment 2
[0214]The following describes the details of a bit interleaver (i.e., a parallel bit interleaver) that satisfies conditions 1A and 2A, given above. In the following description, processing and the units performing such processing are labeled with the same reference numbers wherever applicable.
[0215]In the present document, each group of M / F cyclic blocks or of Q / F constellation words is referred to as a folding section (or as a folding interleaver section).
[0216]When F=1 (i.e., no folding), the folding interleaver sections match the interleaver sections and the bit interleaver is configured identically to the bit interleaver from Embodiment 1.
[0217]Folding occurs when F is an integer greater than one. Embodiment 2 describes an example of folding where F=2.
[0218]FIG. 32 is a block diagram illustrating the configuration of a bit interleaver satisfying Conditions 1A and 2A, when Q=8, M=4, N=12, and F=2, as another Embodiment of the disclosure.
[0219]In FIG. 32, the QC-LDPC codewords are...
embodiment 3
[0266]The following describes an example of an interleaver performing folding in a situation where N is not a multiple of M.
[0267]FIG. 42 illustrates a cyclic block subject to and a cyclic block excluded from (i.e., an excluded block) the interleaving process where F=2, described above. In FIG. 42, the code is 16K LDPC code conforming to the DVB-T2 standard, and the constellation is a 16-QAM constellation. As shown, 44 of the cyclic blocks are subject to interleaving (i.e., blocks 1 through 44), and cyclic block 45, in the last row, is the one cyclic block not subject to interleaving (i.e., the excluded block). The four blackened squares represent the four bits of the first constellation.
[0268]FIG. 43 is a schematic block diagram of a bit interleaver performing folding when N is not a multiple of M. For simplicity, the following values hold: N=13, Q=8, M=4, and F=2.
[0269]The number of folding sections is floor(N / (M / F))=6, and the number of excluded cyclic blocks is rem(N, M / F)=1.
[02...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com