Method for synchronizing an isochronous system with a higher-ranking clock pulse system
a technology of clock pulse and isochronous system, which is applied in the direction of synchronization signal speed/phase control, program control, instruments, etc., can solve the problems of not being able to follow the step size, not being able to suppress the jitter, and not being able to ensure faultless communication with the master clock. , to achieve the effect of suppressing the transmission jitter by the dpll and advantageously implemented in softwar
Active Publication Date: 2015-10-01
SIEMENS AG
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Benefits of technology
The invention provides a method for continuous synchronization and suppression of transmission jitter in a basic clock pulse system. It achieves this by automatically performing individual actions based on a protected and redundant transmission process. The method ensures that failure of individual transmissions does not result in a loss of synchronicity of a component at any time. It also allows for the interface with low-level components of the system and ensures that the process is executed without any errors. The invention is advantageously implemented in software and computer program products, which allows for easy integration with other components of the system. Overall, the invention improves the stability and reliability of the clock pulse system.
Problems solved by technology
This means it is not able to follow the step size during the phase shift (see FIG. 5).
Therefore, for a temporary period, another synchronization method is used, which, although it can follow the phase shift, is not able to suppress the jitter.
The drawback with this known method for synchronizing an isochronous basic clock pulse system with a previously independent topologically higher-ranking clock pulse system is that, due to the abrupt change to the clock pulse period, in addition to the residual jitter, faultless communication with the master clock is no longer guaranteed, for example due to a violation of one of the transmit time slots assigned to the component.
Method used
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[0041]Throughout all the figures, same or corresponding elements may generally be indicated by same reference numerals. These depicted embodiments are to be understood as illustrative of the invention and not as limiting in any way. It should also be understood that the figures are not necessarily to scale and that the embodiments are sometimes illustrated by graphic symbols, phantom lines, diagrammatic diagrams and fragmentary views. In certain instances, details which are not necessary for an understanding of the present invention or which render other details difficult to perceive may have been omitted.
[0042]Turning now to the drawing, and in particular to FIG. 1, there is shown in a schematically greatly simplified illustration a device described in the following as a basic clock pulse system 10 with individual components 12, 14, 16, 18 thereof, wherein one of the components 12-18 functions as a master clock 12 in the basic clock pulse system 10 and wherein all components 12 are...
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A method for synchronizing a basic clock pulse system having a plurality of synchronized components with a higher-ranking clock pulse system includes, in a first step of the synchronization, determining a phase difference between an actual phase of the basic clock pulse system and a nominal phase of the higher-ranking clock pulse system and transmitting the phase difference to the components of the basic clock pulse system and, in a second step of the synchronization, using the determined phase difference as a pilot control for each component, i.e. for the pilot control of a clock pulse generator of each component.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application claims the priority of European Patent Application, Serial No. 14163047.5, filed Apr. 1, 2014, pursuant to 35 U.S.C. 119(a)-(d), the content of which is incorporated herein by reference in its entirety as if fully set forth herein.BACKGROUND OF THE INVENTION[0002]The present invention relates to a method for synchronizing an isochronous system with a previously independent topologically higher-ranking clock pulse system. For differentiation from the higher-ranking clock pulse system, the clock pulse system of the isochronous system, which is to be connected to the higher-ranking clock pulse system, is referred to in the following as an isochronous basic clock pulse system or in short as a basic clock pulse system.[0003]The following discussion of related art is provided to assist the reader in understanding the advantages of the invention, and is not to be construed as an admission that this related art is prior art to t...
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IPC IPC(8): H04L7/04
CPCH04L7/04G05B19/0426G05B2219/34001H04L7/0004H04L7/0008
Inventor GROSS, MARKUSKASDORF, OSWALDSCHLEUSSINGER, ARMINVON DER BANK, MICHAEL
Owner SIEMENS AG