Static random access memory and method thereof

Abstract

A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to a static random access memory (SRAM), and more particularly to a SRAM having an enhanced write margin with scaled power supply voltage.[0003]2. Description of Related Art[0004]Static random access memory (SRAM) is a type of semiconductor memory device that uses a latch to store a bit of information without a need of periodical refreshing as required in a dynamic random access memory (DRAM). A typical SRAM cell is made up of six transistors (6-T), while more transistors (e.g., 8-T) or fewer transistors (e.g., 4-T) may be available. SRAM cells are ordinarily arranged in an array of rows and columns. A word line is connected to, and is used to select, SRAM cells of the associated row. A pair of bit lines is connected to SRAM cells of the associated column, through which the SRAM cell may be read out or written into a bit of information.[0005]As integrated circuits have been scaled...

AI Technical Summary

Benefits of technology

[0009]In view of the foregoing, it is an object of the embodiment of the present invention to provide a SRAM with an enhanced write margin and / or a lower Vmin. In one embodiment, the SRAM provides a negative bit line voltage to improve writability, and furnishes power supply voltage drop to assist in discharging at a bit node.

Problems solved by technology

Conventional SRAM suffers from half-select disturb phenomenon as a word line may simultaneously turn on the SRAM cells adjacent to the selected one of the same row, causing the adjacent SRAM cells to unwanted discharge.

Moreover, as the SRAM cell is selected and read, a read disturb voltage may be undesirably rendered due to voltage divider made of an access transistor and a pull-down transistor.

The word line boosting scheme, however, suffers from low MOS capacitance value in a low-voltage operation, limited cells number associated with a word line, and half-select disturb.

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