Self-aligned gate tie-down contacts with selective etch stop liner

Abstract

A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.

Description

BACKGROUND[0001]Technical Field[0002]The present invention relates to semiconductor processing, and more particularly to a gate tie-down structure that permits gate contacts in active areas and reduces shorts between adjacent contacts and gate conductors.[0003]Description of the Related Art[0004]In conventional complementary metal oxide semiconductor (CMOS) processing, gate contacts are formed over shallow trench isolation (STI) regions. Gate contacts connect a gate line to upper metal layers in device designs. In many instances, providing the gate contacts in STI regions can result in a large amount of chip area being lost.[0005]Gate tie-down structures or regions provide a connection between the gate contact and a source / drain (S / D) region contact. The formation of a gate tie-down structure may result in shorts between a silicide region of the S / D region or with conductive material of an adjacent gate. This is due, in part, to the small margins of dielectric materials between thes...

AI Technical Summary

Problems solved by technology

In many instances, providing the gate contacts in STI regions can result in a large amount of chip area being lost.

The formation of a gate tie-down structure may result in shorts between a silicide region of the S / D region or with conductive material of an adjacent gate.

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