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Method, apparatus, and system for QOS within high performance fabrics

Inactive Publication Date: 2017-08-17
INTEL CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a method for improving the performance and efficiency of high-performance computing (HPC) by using a fabric architecture to interconnect a large number of compute units. The fabric architecture needs to support a variety of advanced protocols and topologies, as well as increasing flexibility and control for traffic separation and quality of service (QoS). The technical effects of this invention include reducing latencies caused by transferring data over the interconnects between compute nodes and increasing the efficiency of HPC by using a fabric architecture to interconnect a large number of compute units.

Problems solved by technology

One of the performance bottlenecks for HPCs is the latencies resulting from transferring data over the interconnects between compute nodes.

Method used

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  • Method, apparatus, and system for QOS within high performance fabrics
  • Method, apparatus, and system for QOS within high performance fabrics
  • Method, apparatus, and system for QOS within high performance fabrics

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Embodiment Construction

[0066]Embodiments of methods and apparatus for implementing Quality of Service (QoS) within high performance fabrics are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0067]Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specificatio...

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Abstract

Method, apparatus, and systems for implementing Quality of Service (QoS) within high performance fabrics. A multi-level QoS scheme is implemented including virtual fabrics, Traffic Classes, Service Levels (SLs), Service Channels (SCs) and Virtual Lanes (VLs). SLs are implemented for Layer 4 (Transport Layer) end-to-end transfer of fabric packets, while SCs are used to differentiate fabric packets at the Link Layer. Fabric packets are divided into flits, with fabric packet data transmitted via fabric links as flits streams. Fabric switch input ports and device receive ports detect SC IDs for received fabric packets and implement SC-to-VL mappings to determine VL buffers to buffer fabric packet flits in. An SL may have multiple SCs, and SC-to-SC mapping may be implemented to change the SC for a fabric packet as it is forwarded through the fabric, while maintaining its SL. A Traffic Class may include multiple SLs, enabling request and response traffic for an application to employ separate SLs.

Description

RELATED APPLICATIONS[0001]This application is a Continuation of U.S. patent application Ser. No. 14 / 139,930, filed on Dec. 24, 2013, entitled “METHOD, APPARATUS, AND SYSTEM FOR QOS WITHIN HIGH PERFORMANCE FABRICS” which is hereby incorporated herein by reference in its entirety.BACKGROUND INFORMATION[0002]High-performance computing (HPC) has seen a substantial increase in usage and interests in recent years. Historically, HPC was generally associated with so-called “Super computers.” Supercomputers were introduced in the 1960s, made initially and, for decades, primarily by Seymour Cray at Control Data Corporation (CDC), Cray Research and subsequent companies bearing Cray's name or monogram. While the supercomputers of the 1970s used only a few processors, in the 1990s machines with thousands of processors began to appear, and more recently massively parallel supercomputers with hundreds of thousands of “off-the-shelf” processors have been implemented.[0003]There are many types of HP...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04L12/851H04L12/931H04L29/06H04L47/2466H04L47/2491H04L47/31H04L47/36H04L49/111
CPCH04L47/2425H04L49/70H04L69/22H04L49/358H04L47/2458H04L47/2491H04L47/2408H04L49/3045H04L49/112H04L49/111H04L49/30H04L49/10
Inventor RIMMER, TODDLOVETT, THOMAS D.CHENG, ALBERT
Owner INTEL CORP
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