Semiconductor layout structure

Abstract

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to a semiconductor layout structure, and more particularly, to a semiconductor layout structure for static random access memory (hereinafter abbreviated as SRAM) cells.2. Description of the Prior Art[0002]In recent years, with widespread use of mobile terminal equipment, digital signal processing in which bulk data such as sounds or images is processed at high speed has been increasingly important. SRAM, which is capable of high-speed access processing, holds an important place as a semiconductor memory device to be mounted on such mobile terminal equipment.[0003]Each of SRAM cells include a bistable circuit, which does not require refreshing. The switching speed of each bistable circuit is determined by the resistance and capacitance of the control electrodes of the transistors and the connection of the transistors within the circuit, thereby determining the slew rate of its output voltage. In a...

AI Technical Summary

Benefits of technology

This layout structure prevents electrical shorts from impacting the circuit devices in the cell edge region by isolating enlarged outer dummy contacts / gates with gaps, ensuring the integrity of the SRAM cell arrays during fabrication.

Problems solved by technology

In applying prior design layout rules, however, problems arose during the fabrication of high-density small-sized SRAM cell arrays: Due to pattern density effect, after patterning, the sizes of metal contact holes at or near a dummy edge cell are larger than the sizes of other metal contact holes within the dense area of a bit cell.

What's more adverse is that optical proximity correction (hereinafter abbreviated as OPC) will even enlarge the sizes of these metal contact holes because they are near iso area (the area with relative lower pattern density).

As a result, the enlarged contact will contact the dummy gate and thus electrical current may go short through the dummy gate.

Such kind of undesirable electrical short is extremely damaging to the formed circuit devices.

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