Memory device having twin cell mode and refresh method thereof

Abstract

A memory device includes: a memory region including a plurality of word lines; and a refresh control block configured to: sequentially refresh the plurality of word lines in a manner such that two or more word lines are simultaneously refreshed during a first refresh operation, simultaneously refresh two or more first critical word lines corresponding to a first critical address generated by up-counting a target address during a second refresh operation, and simultaneously refresh two or more second critical word lines corresponding to a second critical address generated by down-counting the target address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0142533, filed on Oct. 30, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND1. Field[0002]Various exemplary embodiments of the present invention relate to a semiconductor design technique, and more particularly, to a memory device having a twin cell mode and a refresh method of the same.2. Description of the Related Art[0003]Each memory cell of a memory device generally includes a cell transistor functioning as a switch and a cell capacitor for storing charges (i.e., data). Whether data is in a ‘high logic’ level (i.e., logic ‘1’) or a ‘low logic’ level (i.e., logic ‘0’) is decided based on whether the cell capacitor included in the memory cell stores the charges or not, that is, whether a terminal voltage of the cell capacitor is high or low.[0004]Since the ...

AI Technical Summary

Benefits of technology

The present invention provides a method to refresh a memory device that prevents the hammer phenomenon in a twin cell mode. The technical effect of this method is to improve the reliability and performance of the memory device.

Problems solved by technology

However, due to a leakage current caused by a PN junction of a transistor, the initial amount of charges stored in a cell capacitor may be eventually vanish.

Hence, the data stored in the cell capacitor may be lost.

Meanwhile, when the amount of charges stored in a memory cell is affected by an active-precharge operation on a word line adjacent to a word line coupled to the memory cell, data of the memory cell may deteriorate in a shorter time than the interval of the refresh operation.

Such influences may reduce the retention time of these memory cells.

However, heretofore memory devices operating in a twin cell mode use generally inefficient refresh methods that do not adequately address the row hammer phenomenon.

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