Method for controlling time point for data output in synchronous memory device

Abstract

Disclosed is a method for controlling a time point for data output in a synchronous memory device, which varies a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous memory device. In other words, the time point to generate the internal read command when CAS latency corresponds to 2N+2 (N=0, 1, 2, . . . ) is delayed by 1tCK as compared with the time point to generate the internal read command when CAS latency corresponds to 2N+1, and the 1tCK is a period of an external clock applied to the synchronous memory device.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a method for controlling a time point for data output in a synchronous memory device, and more particular to a method for controlling a time point for data output in a synchronous memory device according to CAS latency.[0003]2. Description of the Prior Art[0004]As generally known in the art, a memory device such as a DDR SDRAM generates a plurality of control signals (e.g., OE00, OE10, OE30, and OE50 shown in FIG. 1E) used for controlling the operation of a data output driver according to CAS latency. Conventionally, these control signals are sequentially generated. In other words, the control signals are generated in the order of OE00, OE10, OE20, OE30, OE40 and OE50. For reference, the OE20 is generated with delay of 1tCK (1tCK is a period of an internal clock signal) as compared with the OE10, the OE30 is generated with delay of 1tCK as compared with the OE20, and the OE40 is generate...

AI Technical Summary

Benefits of technology

The present invention provides a method for controlling the time point for data output in a synchronous memory device. The method involves generating control signals with a time difference of 2tCK when the operation frequency increases. The method also allows for the output of data by selecting one of the control signals generated with a time interval of 2tCK when CAS latency is an odd number and delaying the time point of a read command by a time interval of 1tCK when CAS latency is an even number. The method further involves using a signal obtained by dividing aDDR clock signal in the two-division ratio to generate a control signal with a time interval of 2tCK. The method allows for the control of data output in a synchronous memory device with CAS latency of even or odd numbers.

Problems solved by technology

This collision may cause malfunction when the memory device outputs data.

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