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Power supply circuit and semiconductor memory

a power supply circuit and semiconductor technology, applied in the direction of logic circuits, instruments, pulse techniques, etc., can solve the problems of low set potential ripples, unalloyed cell characteristics, and increased ripples of the output of the boosting circui

Active Publication Date: 2009-06-23
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the voltage dividing resistor has a large resistance, ripples increase with the operation delay of the comparator amplifier circuit and the boosting capability of the boosting circuit.
However, the cell characteristics are not all uniform and the cells have different writing potentials enabling writing.
There is a problem that when the set potential is changed, as described above, the ripples of the output of the boosting circuit increase at a low set potential.
However, as described above, during a writing operation on a cell having a low potential enabling writing, when the voltage dividing resistors of the voltage detecting circuit are adjusted to set a low output of the boosting circuit, the conventional circuit has large ripples and deteriorates the characteristics of writing on memory cells.

Method used

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  • Power supply circuit and semiconductor memory
  • Power supply circuit and semiconductor memory
  • Power supply circuit and semiconductor memory

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Experimental program
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first embodiment

[0062]FIG. 1 shows the main configuration of a power supply circuit 100 according to a first embodiment which is an aspect of the present invention. FIG. 2 shows an example of a boosting circuit applied to the power supply circuit of FIG. 1. FIG. 3 shows an example of a voltage detecting circuit applied to the power supply circuit of FIG. 1.

[0063]As shown in FIG. 1, the power supply circuit 100 for outputting different set potentials in response to control signals N1 and N2 includes an output terminal 1 for outputting the set potentials, a boosting circuit 2 for boosting, in response to an input of a boosting clock signal CLK1, a voltage supplied from a power supply VCC and outputting the boosted voltage to the output terminal 1, and a control circuit 3 for outputting the control signals N1 and N2.

[0064]A load connected to the output terminal 1 includes nonvolatile memories such as a NAND EEPROM, a NOR EEPROM, a DINOR EEPROM, and an AND EEPROM and circuits and the like requiring a p...

second embodiment

[0118]The first embodiment described the configuration in which the reference clock is generated by the clock generating circuit.

[0119]In the present embodiment, a configuration using an existing reference clock will be described.

[0120]FIG. 6 shows the main configuration of a power supply circuit 300 according to a second embodiment which is an aspect of the present invention. The same reference numerals as those of FIG. 1 indicate the same configurations as the first embodiment.

[0121]As shown in FIG. 6, the power supply circuit 300 includes a frequency switching circuit 7 instead of the clock generating circuit. Other configurations are the same as those of the first embodiment.

[0122]The frequency switching circuit 7 includes a frequency dividing circuit 7a, a first multiplexer 7b, and a second multiplexer 7c.

[0123]The frequency dividing circuit 7a divides a reference clock signal CLK3 (e.g., ½, ¼, ⅛ and 1 / 16) and outputs a plurality of frequency divided clock signals CLK4 having ...

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Abstract

A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-310240, filed on Nov. 16, 2006, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a power supply circuit including a boosting circuit for boosting a power supply voltage and a semiconductor memory including the power supply circuit.[0004]2. Background Art[0005]Conventionally, for example, a semiconductor memory such as a NAND flash memory includes a power supply circuit for boosting a power supply voltage through a boosting circuit and supplying the power supply voltage.[0006]For example, a semiconductor memory such as a NAND flash memory requires a higher potential than a power supply voltage because data is written, deleted, and read in the semiconductor memory. Thus such a semiconductor memory includes a boost...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C5/14
CPCG11C5/14G11C16/30
Inventor NAKAI, JUNTAKEYAMA, YOSHIKAZU
Owner KIOXIA CORP