Thin film transistor array having improved connectivity between shorting bar and data lines

Abstract

A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority to, and the benefit of, Korean Patent Application No. 10-2011-0062438 filed in the Korean Intellectual Property Office on Jun. 27, 2011, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002](a) Field of the Invention[0003]Embodiments of the present invention relate generally to flat panel displays. a thin film transistor array panel and a manufacturing method thereof.[0004](b) Description of the Related Art[0005]A liquid crystal display, which is a popular type of flat panel display, typically includes two display panels having electrodes, and a liquid crystal layer interposed between the two display panels. The display controls the amount of light transmitted by applying voltage to the electrodes, thus rearranging liquid crystal molecules of the liquid crystal layer.[0006]One of the two display panels constituting the liquid crystal display is a thin film trans...

AI Technical Summary

Benefits of technology

This design reduces performance deterioration and display quality issues by minimizing etching speed variations and static electricity influence, enabling more reliable quality testing and defect detection.

Problems solved by technology

Meanwhile, as display devices increase in size, the size of the thin film transistor array panel also increases.

However, in this case, in an etching process for forming data lines, etching speed may vary as between data lines that are connected and data lines that are not connected, which results in a thickness difference in the lower layers of the data lines.

This may compromise the performance of a thin film transistor of a thin film transistor array panel or compromise display quality, resulting in undesirable phenomena such as vertical lines or the like.

In this case, the influence of static electricity increases, and the thin film transistor thus typically cannot undergo a quality test, therefore allowing a greater number of defects.

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