Digital-to-time converter

Abstract

A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The present invention is related to data converters and more particularly to digital-to-analog converters.[0003]2. Description of the Related Art[0004]In general, a digital-to-time converter is a digital-to-analog data converter that generates an output signal having a period or edge delay based on a digital control word and a reference clock signal. For example, a clock divider circuit is a digital-to-time period converter that generates an output clock signal based on a reference clock signal and a digital control word indicating a divide ratio (e.g. an integer divide ratio or a fractional divide ratio). The analog output is the period of the output clock signal. The output clock period is based on the digital control word and the clock period of the reference clock signal. The output clock signal has a digitally-defined, full-scale range and a least-significant bit clock period.[0005]A typical integer clock frequency divider is a dig...

AI Technical Summary

Problems solved by technology

The analog quantization error of the dithering noise-shaped integer control signal causes substantial deterministic jitter that dominates the jitter performance.

As a result, the system is more dependent on voltage-controlled oscillator phase noise performance which can often translate into higher power consumption.

In addition, the low loop bandwidth of the clock synthesizer reduces its usefulness in data communication applications to supporting significantly lower data rates than might otherwise be desired.

However, an input integer divider provides frequency resolution at the expense of phase noise.

As the frequencies of ckin and ckout increase, the target clock period decreases and jitter introduced by the digital-to-time converter circuits become a larger fraction of the target clock period, thereby causing output clock signals from conventional clock synthesizer designs to fail to meet target performance specifications.

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