Two-dimensional pyramid filter architecture

Abstract

An integrated circuit according to the present invention, which includes: a two-dimensional cone filter architecture with an order of 2N-1, where N is a positive integer greater than 3; the two-dimensional cone filter with an order of 2N-1 The architecture operates to generate at least the following signals at each clock cycle: a tapered filtered output signal corresponding to the output signal produced by four one-dimensional tapered filters of order 2N-1; a tapered filtered output signal corresponding to the output signal produced by four one-dimensional tapered filters of order [2 (N-1)-1] The output signal generated by four two-dimensional cone filters or one two-dimensional cone filter and represented by a signal sample matrix of order [2(N-1)-1] a tapered filtered output signal; wherein each output signal in the two-dimensional tapered filter architecture is summed at each clock cycle of the two-dimensional tapered filter architecture.

Description

[0001] related application [0002] This patent application is related to U.S. Patent Application Serial No. 09 / 754684, filed January 3, 2001, by Tinku Acharya, entitled "Multiplierless Pyramid Filter"; Tinku Acharya, entitled "Two-Dimensional Pyramid Filter Architecture", U.S. Patent Application, filed March 26, 2001 (attorney docket no. 042390.P11275); U.S. Patent Application, filed March 28, 2001, entitled "Conical Filter" application (Attorney Docket No. 042390.P11211); and Tinku Acharya's U.S. Patent Application (Attorney Docket No. 042390.P11211), filed March 2001, entitled "Two-Dimensional Conic Filter Architecture," These patent applications are assigned to the assignee of the present invention and are hereby incorporated by reference into this specification. technical field [0003] The present disclosure relates to two-dimensional pyramid filters. Background technique [0004] In image processing, it is often desirable to decompose an image, such as a color image...

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