Semiconduetor storage device based on pseudo-unit method

Abstract

A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

Description

technical field [0001] The present invention relates generally to semiconductor memory devices, and more particularly to semiconductor memory devices operating based on a pseudo-cell method. Background technique [0002] In DRAM (Dynamic Random Access Memory), a pair of bit lines are precharged to a potential midway between the power supply potential and ground potential, then data is read to one bit line, and the paired bits are then amplified by using a sense amplifier The potential difference between the wires is used to read the data. As the power supply potential has decreased in recent years, it has become increasingly difficult to generate a stable intermediate potential between the power supply potential and the ground potential. Therefore, some technologies using the power supply potential or the ground potential as the pre-charging potential have been developed. Methods of reading data in these technologies include pseudo-cell methods. [0003] FIG. 1 is a circu...

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Problems solved by technology

As a result, the reference potential used for the data read operation fluctuates according to the access interval, thereby causing a problem of reduction of the data-read margin (data-read margin)

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