Semiconductor device, circuit and display device using said device and its driving method

A semiconductor and circuit technology, applied in the driving field of semiconductor devices, can solve problems such as steep threshold changes between circuits, unfixable output, and readout errors

Active Publication Date: 2006-03-22
GOLD CHARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the inventors have faced the problem that readout errors frequently occur when reading out signals from memory cells.
[0042] That is, the instability problem of not being able to fix whether the output goes high or low in a wide range such as V2<ΔV<V1 is a problem different from the steep threshold variation between circuits that is usually seen as a problem The problem
[0141] As mentioned above, the problem revealed is that, in a polysilicon TFT integrated circuit, operation failure occurs due to hysteresis effect

Method used

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  • Semiconductor device, circuit and display device using said device and its driving method
  • Semiconductor device, circuit and display device using said device and its driving method
  • Semiconductor device, circuit and display device using said device and its driving method

Examples

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Effect test

no. 1 example

[0314] Figure 16 is a flowchart showing a method for driving the latch circuit according to the first embodiment of the present invention. The latch circuit used to explain this driving method is the same as Figure 11 The illustrated latch type sense amplifier circuit composed of n-channel MOS transistors is the same. That is, the latch circuit of the present invention includes a polysilicon TFT N1 (4901a) and a transistor N2 (4901b) whose sources are commonly connected. The gate of TFT N1 is connected to the drain of transistor N2, and is also connected to capacitor C2. The gate of TFT N2 is connected to the drain of transistor N1, and is also connected to capacitor C1.

[0315] The latch circuit is driven as follows: In the first period (active period) (5001), using the electrical characteristics of the MOS transistors (4901a and 4901b), signals necessary for circuits other than the latch circuit not shown are output, And in the second time period (idle time period) (5...

no. 2 example

[0406] Although the example in which the VDS of the MOS transistor is 0 and no current flows when the body potential reset pulse is applied has been shown in the first embodiment, the same circuit as in the first embodiment is used in the second embodiment of the present invention ( like Figure 11 circuit shown), and perform with Figure 16 different drivers.

[0407] Figure 26 is a flowchart showing a method for driving the latch circuit of the present invention. its with Figure 16 The difference is that (VDD1-Vt)V is supplied to the node K during the period in which the body potential reset pulse is applied, so that the drain current flows into the MOS transistor to which the body potential reset pulse is being input.

[0408] Here, although the (VDD1-Vt)V supplied to the node K has been described, it is convenient to use in experiments Figure 17 The voltage set by the circuit, therefore, simply applying VDD1 is essentially the same.

[0409] The latch circuit is d...

no. 3 example

[0431] In this embodiment, a description will be given of a specific example of a latch type sense amplifier circuit to which the driving method of the first embodiment is applied.

[0432]A circuit diagram of the sense amplifier circuit of the present invention is shown in Fig. 28A. The transistor N1 (4901a) and the transistor N2 (4901b) are n-channel polysilicon TFTs, and the transistor N3 is for switching on and off the connection between the source (node ​​K) of the transistors N1 and N2 and the SAN electrode according to the signal SE3. Part of the n-channel polysilicon TFT. The SAN nodes are connected to VSS (eg, 0V).

[0433] Denoted node A is for the drain of transistor N1, and denoted node B is for the drain of transistor N2. Bit line ODD (5301a) is connected to node A through switch M03 (4905a), and the on / off of switch M03 (4905a) is controlled by PAS. In addition, bit line EVN (5301b) is connected to node B through a transfer control part (ie, switch M04) (4905b...

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Abstract

A device excellent in electrical characteristics is provided by suppressing an operation failure owing to a hysteresis effect that occurs in a circuit using MOS transistors having floating bodies. Moreover, sensitivity of a sense amplifier circuit and a latch circuit including these MOS transistors as components is improved. A signal required in a circuit other than a first circuit is outputted by using electrical characteristics of MOS transistors in a first period (effective period), and in a second period (idle period) excluding the first period, between the gate and source of MOS transistors, a step waveform voltage not less than threshold voltages of these MOS transistors is given.

Description

technical field [0001] The present invention relates to a semiconductor device, a circuit and a display device using the semiconductor device, and a driving method of the semiconductor device, more particularly, to a MOS (metal oxide semiconductor) transistors such as polysilicon TFTs (thin film transistors), circuits and display devices using the semiconductor devices, and driving methods of the semiconductor devices. Background technique [0002] Polysilicon TFTs formed on insulating substrates once required expensive quartz substrates for high-temperature processing, and have been applied to small-sized, high-value-added display panels. Afterwards, a technique was developed in which a precursor film was formed by methods such as low-pressure (LP) CVD, plasma (P) CVD, or sputtering, and then laser annealed to polycrystallize it, which is capable of allowing the use of A technology that forms polysilicon TFTs at relatively low temperatures on glass substrates, etc. At the...

Claims

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Application Information

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IPC IPC(8): G09G3/20
CPCG09G3/3648G09G2310/027G09G2300/0408G09G3/3688G09G2310/0289G09G2300/08G09G2310/0297
Inventor 芳贺浩史音濑智彦浅田秀树野中义弘是成贵弘高取宪一
Owner GOLD CHARM LTD
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