High speed zero DC power programmable logic device (PLD) architecture

Abstract

A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells (Fig.3). Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit (330-333), a settable latch (320-323), a signal path means (360A, 360B), and an output logic gate (350). The signal-path means coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block (402-408) for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) (700) which includes an array of word lines (pwd) and bit lines (vcol, pcol) arranged in rows and columns for addressing, an array of OR gates (740), and a plurality of output logic circuits (750).

Description

field of invention [0001] The present invention generally relates to programmable logic devices (PLDs), and more particularly, the present invention relates to high-speed, zero DC power consumption PLD structures. Background of the invention [0002] Programmable logic devices (PLDs) are well known in the art and are widely used to perform complex digital logic functions in the form of sums of products or products of sums. Each PLD basically includes a memory array or matrix functioning as programmable AND gates, readout circuitry, a fixed OR gate array, and output logic circuitry. The array of fixed OR gates can also be a programmable OR array. When the row and column decoders select a particular cell to read or write data from, the sense amplifier in the sense circuit reads information from the selected cell, the fixed OR array, and the output logic circuit to perform logic functions. When this occurs, the bit line connected to the programmable array of the selected cell...

AI Technical Summary

Problems solved by technology

In addition, the sense amplifiers consume a considerable amount of power in normal operation

Also, noise spikes (spikes) often cause the PLD to read incorrect values ​​to its output logic

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