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Chip packing-body

A chip packaging and chip technology, applied in the direction of electrical solid devices, semiconductor devices, semiconductor/solid device components, etc., can solve the problem of polluting chips

Active Publication Date: 2008-05-28
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] However, for the second substrate pads 124, since the total contact surface area of ​​the bumps 130 cannot be increased to be equivalent to the surface area of ​​the surface bonding layer 126 forming the second substrate pads 124, some of them are located on these second substrate pads 124 and The surface bonding layer 126 in a molten state will climb up along the sides of the bumps 130 and toward the chip 110 due to surface tension, thereby contaminating the chip 110

Method used

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Examples

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no. 1 example

[0040] Please refer to figure 2, which shows a schematic cross-sectional view of a chip package according to the first embodiment of the present invention. The chip package 200 of the first embodiment includes a chip 210 , a packaging substrate 220 and a plurality of bumps 230 . The chip 210 has a plurality of chip pads 212 , and the chip pads 212 are arranged on a surface 214 of the chip 210 in an area array, for example. The package substrate 220 has a plurality of first substrate pads 222 , a plurality of second substrate pads 224 and a surface bonding layer 226 , and the first substrate pads 222 and the second substrate pads 224 are disposed on one side of the package substrate 220 . On the surface 228 , the surface bonding layer 226 is disposed on the first substrate pads 222 and the second substrate pads 224 , and the surface bonding layer 226 covers a partial area of ​​each second substrate pad 224 .

[0041] These bumps 230 are respectively disposed between the chip...

no. 2 example

[0057] Please refer to figure 2 and Figure 4 ,in Figure 4 A schematic cross-sectional view of a chip package according to a second embodiment of the present invention is shown. The difference between the chip package 300 of the second embodiment and the chip package 200 of the first embodiment is that the packaging substrate 320 of the chip package 300 includes two solder mask layers M1 and M2 . The function and location of the solder mask layer M2 are the same as those of the above solder mask layer M, and the solder mask layer M1 is disposed on the second substrate pads 324 and has a plurality of openings O, and is disposed on the second substrate pads 324 The surface bonding layer 326 is located within these openings O.

[0058] In addition, the manufacturing method of the chip package 300 is also different from the manufacturing method of the chip package 200 . Figure 5A to Figure 5D draw Figure 4 A schematic diagram of some steps of the manufacturing method of t...

no. 3 example

[0066] Please refer to Figure 4 and Figure 6 ,in Figure 6 A schematic cross-sectional view of a chip package according to a third embodiment of the present invention is shown. The difference between the chip package 400 of the third embodiment and the chip package 300 of the second embodiment lies in the arrangement of the solder mask layer M1' and the surface bonding layer 426 of the package substrate 420 of the chip package 400 . The surface bonding layer 426 is disposed on the first substrate pads 422 and the second substrate pads 424, and the solder mask layer M1' is disposed on the surface bonding layer 426 of the second substrate pads 422, and the solder mask layer M1 'has a plurality of openings O' to expose the surface bonding layer 426 .

[0067] In addition, the manufacturing method of the chip package 400 is also different from the manufacturing methods of the chip packages 200 and 300 .

[0068] Figure 7A to Figure 7D draw Figure 6 A schematic diagram of...

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Abstract

This invention relates to a chip package unit including a chip, a package base plate and multiple convex blocks, in which, the chip has many connecting pads matched to a surface of the chip, the package base plate has many first connecting pads, multiple second connecting pads and a surface connecting layer, these pads are matched to a surface of said package base plate, the surface connecting layer is matched on these pads and covers part areas of the second connecting pads, these convex blocks are matched between the pads and the surface connecting layer, the chip is connected with the package base plate electrically via these convex blocks, each first base plate pad is connected with one convex block electrically and every second pad is connected with at least two of the blocks.

Description

technical field [0001] The present invention relates to a semiconductor element, and in particular to a chip package. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be divided into three stages: IC design, IC process, and IC package. [0003] In the fabrication of integrated circuits, chips are completed through wafer fabrication, integrated circuit formation, and wafer sawing. The chip has an active surface, which generally refers to the surface of the chip with active devices. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further equipped with a plurality of chip pads (chip pads), so that the chips formed by dicing the wafer can be electrically connected to a carrier through the chip pads. (carrier). The carrier is, for example, a leadframe or a package substrate. The chip can be connected to the carrier by wire bonding or flip chip bonding, so that the chip pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488
CPCH01L2224/16225H01L2224/32225H01L2224/73204H01L2924/15184H01L2924/15311H01L2924/00
Inventor 何昆耀宫振越张家榕
Owner VIA TECH INC
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