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Data pickup processing method for logic analyzer and apparatus thereof

一种逻辑分析仪、处理方法的技术,应用在逻辑分析仪的资料撷取处理及其装置领域,能够解决没办法使用者看到波形、无法得知取样时脉时间差等问题

Inactive Publication Date: 2009-02-04
ZEROPLUS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1. There is no way for the user to see the complete waveform after the limitation
[0006] 2. The user cannot know the time difference between the two sampling clocks

Method used

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  • Data pickup processing method for logic analyzer and apparatus thereof
  • Data pickup processing method for logic analyzer and apparatus thereof
  • Data pickup processing method for logic analyzer and apparatus thereof

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0019] Please refer to FIG. 4 , the analyzer 10 includes a control unit 11, a storage unit 12 (such as: SRAM) and a data acquisition device 13, so that the data acquisition device 13 receives the clock signal and the clock limiter. signal, a Qualified Clock can be obtained, and the Qualified Clock can be sent to the aforementioned control unit 11, and the aforementioned control unit 11 will use the Qualified Clock as the sampling clock , and then capture the detection data in the object under test 30, and then store the captured detection data in the storage unit 12, so that after the memory capacity of the storage unit 12 is used up (full), it will be stored in the The detection data in the storage unit 12 are transmitted to the computer system 40 via the transmission interface 20 , and the detection results are displayed on the screen of the computer system 40 .

[0020] Please refer to Fig. 4 and Fig. 5, when obtaining a limited clock pulse, that is, the sampling clock puls...

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PUM

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Abstract

A logic analyzer data retrieving method used in a logic analyzer formed of a control unit, a memory unit, and a data retrieving circuit, is disclosed to include the step of driving the data retrieving circuit of the logic analyzer to receive a time delay default value and to store in a buffer in a time delay circuit, and the step of triggering the preset of a first counter and transferring the default value from the buffer to the first counter to drive the first counter to start counting when a clock qualifier signal entered so as to obtain a complete clock enable signal when the first counter counted up to the default value and the output of the clock enable became low.

Description

technical field [0001] The present invention relates to a method and device for data acquisition and processing of a logic analyzer, especially an analyzer capable of capturing complete clock enable signals, and the analyzer can also allow users to understand two clock enable signals How much time interval between signals. Background technique [0002] By the way, in today’s increasingly digitalized electronic products, the traditional oscilloscope is no longer enough to measure the signals of more than 8 to 16 channels. Although the online simulator (ICE) can solve many digital problems, the real timing problem cannot be solved. Processed by an online simulator that focuses on software development, coupled with the fact that the online simulator is dedicated to a specific microcomputer system, the logic analyzer has become one of the necessary measuring instruments for engineers. It can convert the required data Expressed in a very organized format (Format), the user can e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/00G01R31/28G01R31/3177G11C29/56
CPCG11C29/56G11C2029/5606G01R31/3177
Inventor 郑秋豪郑铭国曾俊峰张宏业
Owner ZEROPLUS TECH CO LTD
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