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Wafer-level burn-in and test cartridge

A chip and test system technology, applied in the field of wafer-level burn-in and test box, can solve the problems of difficult electrical contact of chips, loss of cost of packaging IC, etc.

Inactive Publication Date: 2009-05-27
AEHR测试体系
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Disadvantages of aging packaged IC's are: if the IC fails during burn-in, the added expense of packaging the IC is lost; a very large number of individual components need to be handled; different fixtures are required to complete the same die in many different package types Ageing
Disadvantages of wafer-level burn-in are: the need to handle the wafer carefully; and making electrical contact with the wafer more difficult

Method used

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  • Wafer-level burn-in and test cartridge
  • Wafer-level burn-in and test cartridge
  • Wafer-level burn-in and test cartridge

Examples

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Embodiment Construction

[0036] Figure 1 shows the wafer level burn-in and test cassette of the present invention. The cartridge is indicated generally at 10 and includes a chuck 12 and a probe plate 14 . Chuck 12 and probe plate 14 may be made of any suitable material. In the illustrated embodiment, chuck 12 and probe plate 14 are made of 6061 aluminum.

[0037] The chuck 12 is generally rectangular in shape and includes a centrally raised base 16 . In use, a semiconductor wafer is placed on top surface 18 of susceptor 16 . Mounted to the top surface of the chuck 12 are the lower half 20 of three mechanical linkages which, in use, lock the chuck 12 and probe plate 14 together. In the illustrated embodiment, the mechanical connections are kinematic connectors, which will be combined below Figures 6 to 12 The mechanical connection means are discussed in more detail. A plurality of slots 22 run transversely through the chuck 12 through which air or another fluid is circulated to cool or heat the c...

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Abstract

A cartridge (10) includes a chuck plate (12) for receiving a wafer (74) and a probe plate (14) for establishing electrical contact with the wafer. In use, a mechanical connecting device (90) locks the chuck plate and the probe plate fixed relative to one another to maintain alignment of the wafer and the probe plate. Preferably, electrical contact with the wafer is established using a probe card (50) that is movably mounted to the probe plate by means of a plurality of leaf springs (52). The mechanical connecting device is preferably a kinematic coupling including a male connector (94) and a first and second opposed jaws (122, 124). Each of the jaws is pivotable from a retracted position in which the male connector can be inserted between the jaws and an engaging position in which the jaws prevent withdrawal of the male connector from between the jaws. The male connector is movable between an extended and retracted position, and is biased towards the retracted position. This provides a positive clamping force that pulls the chuck and probe plates together when the mechanical connecting device is engaged. To leaf a wafer into the cartridge, the wafer is placed on the chuck plate, the probe plate is aligned with the wafer, and the chuck plate and the probe plate are locked together. The cartridge can then be removed from the alignment device and placed in a burn-in or test chamber that does not itself require means for aligning the wafer or for providing a probe actuation force. <IMAGE>

Description

[0001] The National Defense Advanced Engineering Research Institute granted support for this invention in part. The US Government may have rights in this invention. technical field [0002] In particular, the present invention relates to cassettes for use in burn-in and / or testing of circuits formed on semiconductor wafers prior to dicing of the wafers. However, the invention is also applicable to the aging or testing of other electrical devices. The invention also relates to a method of loading a probe card in a cassette and aligning it with a semiconductor wafer in the cassette. The invention also relates to the connection means used in the cassette. This invention is related to commonly owned U.S. Patent 5,429,510, issued Jul. 5, 1995 to Barraclough et al., entitled "High Density Interconnect Technology," and Brehm et al., issued Oct. 28, 1997, entitled "Use for Testing Memory Invention in commonly owned US Patent 5,682,472 "Method and System for Programming a Device", t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/316G01R31/28G01R1/04G01R31/26G01R1/06H01L21/66H05K3/00
CPCG01R31/2867G01R31/2831G01R31/2806G01R31/2865G01R31/2886H05K3/4691G01R1/0491G01R31/2863H01L22/00
Inventor F·O·乌赫尔M·C·卡蓬D·P·里士满二世J·安德伯格
Owner AEHR测试体系
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