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Separable grid flash memory cell and its forming method

A memory cell and split gate technology, which is applied in the formation of split gate flash memory, can solve the problems that the efficiency needs to be improved.

Active Publication Date: 2009-09-02
PROMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the efficiency of this erasing method needs to be improved

Method used

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  • Separable grid flash memory cell and its forming method
  • Separable grid flash memory cell and its forming method
  • Separable grid flash memory cell and its forming method

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Experimental program
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Embodiment Construction

[0016] Figure 1 to Figure 7 A schematic cross-sectional process diagram of a split-gate flash memory unit according to a preferred embodiment of the present invention is shown.

[0017] Such as figure 1 As shown, a P-type semiconductor substrate 100 is provided, which includes an N-type source region 80, an N-type drain region 90, and an area between the source region 80 and the drain region 90. A channel region 95 between them. Next, a first insulating layer 102 , a first conductive layer 103 , a second insulating layer 104 , a second conductive layer 105 , and a top cover layer 106 are sequentially formed on the semiconductor substrate 100 . Wherein, the source region 80 and the drain region 90 can be formed after the gate structure is formed.

[0018] The methods for forming the first insulating layer 102 include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, and the like. The above-mentioned first insulating lay...

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PUM

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Abstract

A split gate flash memory unit includes: a semiconductor substrate; a first insulating layer placed on the semiconductor substrate; a floating gate placed on the first insulating layer, wherein the floating gate has The first width; the second insulating layer is placed on the floating gate; a control gate is placed on the second insulating layer; a top cover layer is placed on the control gate, wherein the top cover layer, control The gate and the second insulating layer have the same second width, wherein the second width is smaller than the first width; the third insulating layer is placed on the control gate, the second insulating layer, the floating gate, the first a sidewall of an insulating layer and on the semiconductor substrate; and an erase gate placed on the third insulating layer. Since the floating gate forms a protruding profile that protrudes from the bottom of the control gate, the increased area of ​​the protruding profile changes the charge distribution to form a sharp discharge field, thereby improving the erasing between the floating gate and the erasing gate. efficiency.

Description

technical field [0001] The invention relates to a method for manufacturing a non-volatile memory, in particular to a method for forming a separated gate flash memory with a floating gate with a protruding outline. Background technique [0002] There are many types of non-volatile semiconductor storage elements (Nonvolatile Memory Device), such as erasable and programmable read-only memory (EPROM), UV-erasable and programmable read-only memory (UV-erasable EPROM), electrically erasable And programmable read-only memory (EEPROM), flash memory (Flash Memory), and one-time program erasable and programmable read-only memory (One-time-programmable EPROM), etc. [0003] The gate type of the flash memory can generally be divided into two types: a stack gate structure and a split gate structure. Wherein, the stacked gate structure includes a tunnel oxide layer formed on the substrate in sequence, a polysilicon layer 1 (poly 1) as a floating gate, an oxide / nitride / oxide (Oxide-Nitrid...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8247H01L27/115H10B69/00
Inventor 傅景鸿廖宏魁卢建中
Owner PROMOS TECH INC