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Separable grid flash memory cell and its forming method

A storage unit and split gate technology, which is applied in the formation of split gate flash memory, can solve the problems that the efficiency needs to be improved.

Active Publication Date: 2007-05-23
PROMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the efficiency of this erasing method needs to be improved

Method used

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  • Separable grid flash memory cell and its forming method
  • Separable grid flash memory cell and its forming method
  • Separable grid flash memory cell and its forming method

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Embodiment Construction

[0016] 1 to 7 are schematic cross-sectional process diagrams of a split-gate flash memory cell according to a preferred embodiment of the present invention.

[0017] As shown in FIG. 1, a P-type semiconductor substrate 100 is provided, which includes an N-type source region 80, an N-type drain region 90, and the source region 80 and the drain region. A channel region 95 between regions 90. Next, a first insulating layer 102 , a first conductive layer 103 , a second insulating layer 104 , a second conductive layer 105 , and a top cover layer 106 are sequentially formed on the semiconductor substrate 100 . Wherein, the source region 80 and the drain region 90 can be formed after the gate structure is formed.

[0018] The methods for forming the first insulating layer 102 include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, and the like. The above-mentioned first insulating layer 102 is, for example, silicon oxide, and i...

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Abstract

The invention relates to a separated grid flash memory unit, which comprises semi-conductive substrate, the first insulated layer above the substrate; one floating grid above the first insulated layer with the first width; the second insulated layer above the grid; one control grid above the second insulated layer; one top cover above the control grid; the top cover, control grid and the second insulated layer have same second widths smaller than the first width; the third insulated layer is at the side walls of control grid, second insulated layer, floating grid, and the first insulated layer, and the bottom of substrate; one erasing grid is on the third insulated layer; since the floating grid forms one protrusion on the bottom of control grid, to change the charge distribution to form one sharp discharge, and improve the erase efficiency between floating grid and erasing grid.

Description

technical field [0001] The invention relates to a method for manufacturing a non-volatile memory, in particular to a method for forming a separated gate flash memory with a floating gate with a protruding outline. Background technique [0002] There are many types of non-volatile semiconductor storage elements (Nonvolatile Memory Device), such as erasable and programmable read-only memory (EPROM), UV-erasable and programmable read-only memory (UV-erasable EPROM), electrically erasable And programmable read-only memory (EEPROM), flash memory (Flash Memory), and one-time program erasable and programmable read-only memory (One-time-programmable EPROM), etc. [0003] The gate type of the flash memory can generally be divided into two types: a stack gate structure and a split gate structure. Wherein, the stacked gate structure includes a tunnel oxide layer formed on the substrate in sequence, a polysilicon layer 1 (poly 1) as a floating gate, an oxide / nitride / oxide (Oxide-Nitrid...

Claims

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Application Information

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IPC IPC(8): H01L21/8247H01L27/115
Inventor 傅景鸿廖宏魁卢建中
Owner PROMOS TECH INC