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Arithmetic operation unit, information processing apparatus and arithmetic operation method

A technology of information processing equipment and arithmetic operations, applied in the direction of electrical digital data processing, digital data processing components, calculations, etc., can solve the problem of increased delay, prevent the increase of delay, reduce hardware resources, and increase clock frequency Effect

Inactive Publication Date: 2009-09-30
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0035] However, when method (1) is adopted, the delay becomes larger

Method used

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  • Arithmetic operation unit, information processing apparatus and arithmetic operation method
  • Arithmetic operation unit, information processing apparatus and arithmetic operation method
  • Arithmetic operation unit, information processing apparatus and arithmetic operation method

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Embodiment Construction

[0068] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0069] [1] Embodiment of the present invention in the case of single-precision arithmetic

[0070] First, refer to figure 1 The shown block diagram depicts the structure of a floating-point multiply-adder according to an embodiment of the present invention. Incidentally, like reference numerals in the drawings designate like or corresponding components, and thus their detailed descriptions are partially omitted here.

[0071] Such as figure 1 As shown, the floating-point multiplication adder 1 includes a right shifter (rectifier) ​​10, a multiplier [CSA (carry-save adder) tree] 11, a CSA (carry-save adder) 12, an absolute value adder (Abs . adder) 13 , shift amount calculator [L.Z. (leading zero) predictor] 20 , normalizer (left shifter) 30 , rounder 40 and sticky bit generator 50 .

[0072] The floating-point multiply-adder 1 supports single-precisio...

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Abstract

An arithmetic operation unit that generates information representing whether an arithmetic operation result has been shifted when the arithmetic operation result is normalized, the arithmetic operation unit comprising: an arithmetic logic unit for outputting an arithmetic operation result; A normalizer for bitizers, which normalizes the results of arithmetic operations; a shift amount calculator, which calculates multiple shift amounts for multiple shifters; a predictor, which is used for using all the plurality of shift amounts to generate intermediate information which is a prediction result of whether the arithmetic operation result is to be shifted when the arithmetic operation result is normalized; and a generator for generating the information by using the intermediate information. The cycle time required to generate sticky bits is reduced to generate sticky bits efficiently, and hardware resources for generating sticky bits are reduced.

Description

technical field [0001] The present invention relates to a technique for rounding the result of an arithmetic operation by using a sticky bit in a floating-point multiply-adder (FMA) in an arithmetic operation unit. More specifically, the present invention relates to techniques for efficiently obtaining sticky bits when using predictive theory, wherein predictive theory determines that within an error range of a predetermined bit (for example, a "1" bit) to use in the rounding process of the result of an arithmetic operation The normalized shift amount of . Background technique [0002] The floating-point multiply-adder (FMA) used here is, for example, constructed as Figure 12 shown. Figure 12 The floating-point multiply-adder 100 shown includes a right shifter (aligner) 10, a multiplier [CSA (carry-save adder) tree] 11, a CSA (carry-save adder) 12, an absolute value adder Adder (Abs. Adder) 13, Shift Quantity Calculator [L.Z. (Leading Zero) Predictor] 20, Normalizer (Left...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/302
CPCG06F7/483G06F7/49952G06F7/74G06F7/5443G06F7/49957G06F5/012G06F2207/382G06F7/00
Inventor 田尻邦彦
Owner FUJITSU LTD
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