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Shallow groove isolated forming process

A forming process and shallow trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of reduced efficiency, increased cost, and increased overall complexity of the shallow trench isolation forming process, and improved production. Efficiency, cost reduction effect

Inactive Publication Date: 2009-12-16
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Relatively complex shallow trench Liner Oxidation or 2 times Liner Oxidation increases the overall complexity of the shallow trench isolation forming process, which increases the cost and reduces the production efficiency

Method used

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  • Shallow groove isolated forming process
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  • Shallow groove isolated forming process

Examples

Experimental program
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Effect test

Embodiment Construction

[0015] refer to Figure 1-Figure 6 ,in Figure 1-Figure 5 A process flow of a shallow trench isolation forming method according to an embodiment of the present invention is shown; Figure 6 is a flow chart of a shallow trench isolation forming method according to an embodiment of the present invention. The present invention provides a shallow trench isolation forming process 100, including:

[0016] 102. Active area pad oxidation and silicon nitride deposition. refer to figure 1 As shown, pad oxidation is performed on the active area (ActiveArea) to form a pad oxide layer PAD, and then silicon nitride SiN is deposited on the pad oxide layer PAD.

[0017] 104. Dielectric antireflection film deposition. refer to figure 2 In the shown structure, after the silicon nitride SiN is deposited, the dielectric antireflective coating (Dielectric AntiReflecting Coating, DARC) is continuously deposited on the SiN.

[0018] 106. Active area pad oxide layer, dielectric anti-reflectiv...

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Abstract

The invention discloses a shallow trench isolation forming process, including: active area liner oxidation and silicon nitride deposition; dielectric anti-reflection film deposition; active area liner oxide layer, dielectric anti-reflection film and active Area etching, wherein the etching for the active area is soft etching to form a slope in the active area; spacer oxidation, deposition and etching; shallow trench etching; shallow trench inner wall isolation layer oxidation and high-density plasma oxidation deposition. Adopting the technical scheme of the present invention, the slope is formed by soft etching of the active region, so that a uniform circular top angle can be easily obtained when performing shallow trench etching, and the complicated shallow trench etching in the prior art is avoided Steps and multiple Liner Oxidation steps reduce costs and increase production efficiency.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, more specifically, to a shallow trench isolation forming process. Background technique [0002] As the feature size of semiconductor devices continues to shrink, the isolation area between devices must also be reduced accordingly. At present, the most widely used isolation technology in the manufacturing process of integrated circuits above 0.35 microns is the LOCOS (Local oxide isolate) technology. Although the process has a long history and is relatively mature, due to the field oxidation process, the depth of the oxide film and the bird's beak effect on the active area at the edge of the field due to oxidation limit the application of this technology. further application. Shallow trench isolation (STI: shallow trench isolate) technology is an isolation technology developed to correspond to a deep submicron process below 0.35 microns. Although shallow trench isolation technology has b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
Inventor 吴佳特邬瑞彬
Owner SEMICON MFG INT (SHANGHAI) CORP