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Technique for programming clocks in automatic test system

An automatic test system and clock technology, applied in the direction of electronic circuit test, digital circuit test, electrical measuring instrument components, etc., can solve the problems of frequency and time consumption that cannot be guaranteed for final use

Inactive Publication Date: 2009-12-30
TERADYNE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This task is often relegated to a time-consuming process of trial and error
Furthermore, nothing about this artificial technique ensures that the frequency ultimately used is the closest practicable frequency satisfying the ratio constraint to the originally desired frequency
Therefore, current technology does not necessarily minimize the frequency error

Method used

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  • Technique for programming clocks in automatic test system
  • Technique for programming clocks in automatic test system
  • Technique for programming clocks in automatic test system

Examples

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Embodiment Construction

[0036] figure 1 is a simplified equivalent block diagram of the timing system 100 with which a system for configuring clocks can be used. The timing system 100 corresponds to the Catalyst TM A timing system for a test system manufactured by Teradyne, Inc., of Boston, MA. In the timing system, the 10MHz crystal oscillator 110 is multiplied by the PLL 112 to generate a 100MHz reference clock. The reference clock is multiplied by the K multiplier 114 to generate an ultra-high resolution optical reference clock (ORC). This ORC has a fixed schema and a variable schema. In fixed mode, K=500,000,000, which corresponds to 50,000 THz (1Terahertz=10 12 Hz) ORC frequency. In variable ORC mode, K is allowed in 2 28 and 2 29 , which corresponds to an ORC ranging between approximately 26,844 THz and 53,687 THz. Fixed ORC schemas are generally easier to program than variable ORC schemas due to the use of rounded integers. However, being more flexible, the variable ORC mode more ofte...

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Abstract

A system and method for configuring an automatic test system to produce a plurality of clocks from a reference clock includes a user interface and software. The user interface receives a plurality of inputs that specify desired frequencies of the plurality of clocks. In response to a command from the user interface, the software calculates values for dividers coupled to the reference clock, for deriving each of the desired frequencies from the reference clock. According to one embodiment, the desired frequencies form ratios that must be met to satisfy coherence. In calculating the divider values, the software minimizes frequency errors while precisely preserving the required ratios.

Description

[0001] Cross references to related applications: [0002] No application applies. [0003] Statement of the federally funded research and development program involved: [0004] No statement applicable. [0005] Microform appendices involved: [0006] No Microform Addendum applicable. technical field [0007] The present invention relates generally to automatic test equipment (ATE) for electronic devices, and, more particularly, to techniques for programming multiple clocks in an automatic test system. Background technique [0008] Relevant field description including information disclosed under 37 C.F.R. 1.97 and 1.98 [0009] ATE systems typically use multiple clocks for testing electronic devices. In a common test script, three or more clocks are used—for example, a digital clock, a source clock, and a capture clock. The digital clock defines the rate at which the digital I / O applies a digital signal to the DUT (device under test: device under test), or samples a dig...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/319G01R31/28
CPCG01R31/31922G01R1/025G01R31/31912
Inventor 吉尔伯特·R·里泽
Owner TERADYNE
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