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Method for writing a data line into an l2 cache

A cache, data line technology, applied in electrical digital data processing, memory systems, memory architecture access/allocation, etc., can solve problems such as performance degradation

Inactive Publication Date: 2007-08-08
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this also causes all other copies of the line to be evicted from other caches
Now, if the data is only "read" by two processors, that is, it is shared data, the line will suffer from a "tug of war" between the caches, which reduces performance

Method used

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  • Method for writing a data line into an l2 cache
  • Method for writing a data line into an l2 cache

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Embodiment Construction

[0012] A multiprocessor system with multiple independent processors is described here. Each processor has an associated L1 cache, and the multiprocessor system has at least one shared main memory and at least one shared L2 cache. The methods described herein involve writing a data line into an L2 cache that includes a local change bit indicating the installed state of the data line.

[0013] A local change bit is a bit associated with each line stored in any cache that maintains line-specific local change status information for each line stored in a particular cache of each cache. Specifically, when resident in a particular cache of the caches, the local change bits indicate whether a particular line of lines stored in that particular cache has been modified by any one of the processors in the multiprocessor system.

[0014] FIG. 1 shows a processor system 101 including a processor 111 and an L1 cache 113 , an L2 cache 121 and a main memory 131 . Applications running on the ...

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Abstract

Using local change bit to direct the install state of the data line. A multi-processor system that having a plurality of individual processors where each of the processors has an associated L1 cache, and the multi-processor system has at least one shared main memory, and at least one shared L2 cache. The method described herein involves writing a data line into an L2 cache comprising and a local change bit to direct the install state of the data line.

Description

technical field [0001] The present invention relates to memory caches in which portions of data stored in slower main memory are transferred between one or more requesting processors and main memory to faster memory, in particular by local change bits. bit) to direct selected data from main memory into cache. Background technique [0002] When data is first referenced in a multiprocessor system, it is difficult to predict whether that data will eventually change, eg, by requesting a processor's "store" or simply "read". If data is installed in the cache in a "read" state, and the processor does not "store" the line, additional latency is required to ensure cache coherency. That is, all other copies of the line must be removed from other caches. [0003] On the other hand, it can be considered that one data line will be changed, for example via "storage", and that line is installed "exclusively" to the processor. However, this also causes all other copies of the line to be...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F2212/507G06F12/0811G06F12/0815
Inventor 凯瑟林·M.·杰克逊麦柏乾基思·N.·兰斯顿小亚瑟·J.·奥内尔戴维·S.·赫顿
Owner INT BUSINESS MASCH CORP