Mixed signal integrated circuit
A technology of integrated circuits and circuits, applied in the direction of generating/distributing signals, electrical components, automatic power control, etc., can solve the problems of high cost of analog circuits, affect the design of analog circuits, and be difficult to implement, and achieve the effect of reducing the amount of interference
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[0029] The PLL clock buffer circuit shown in Figure 3 is based on the JEDEC standard specification for this circuit for registered DDR2 DIMM applications (JESD82-11), so its configuration and operation will not be described in detail here. Figure 4 shows a modified version of this circuit according to an embodiment of the invention.
[0030] In the known circuit in FIG. 3 , the SSM requires an external clock signal along input line 22 . In contrast, in the embodiment of the invention shown in FIG. 4, the SSM 20 is replaced by the input latch 29 and the ASM 30, and the clock signal is no longer required, thereby removing a significant source of interference accompanying the digital circuitry in the integrated circuit. .
[0031] The PLL clock buffer circuit distributes the differential clock input pair 24 to the ten differential clock output terminals Y0 to Y9 and their inverting terminals. These clock outputs are controlled by 4 input signals, the positive supply AV DD , "O...
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