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Integrated circuit self-test architecture

An integrated circuit, self-testing technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of complex interface connection and so on

Inactive Publication Date: 2007-10-31
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] This pre-considered SIST structure has the disadvantage that the interfacing between the SIST monitor and the controller is complex

Method used

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  • Integrated circuit self-test architecture
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Embodiment Construction

[0016] Embodiments of the present invention are directed to providing simplified communication with monitors on an integrated circuit, and allowing saving of area occupied by monitors on an integrated circuit.

[0017] As shown in Figure 3, in an embodiment of the invention, the means for providing communication with the monitor is implemented as a shift register. In FIG. 3 the integrated circuit 1 is provided with three functional blocks 22 , 24 and 26 . Each of these functional blocks performs a function suitable for the operation of the integrated circuit. It should be understood that the integrated circuit may be provided with any number of functional blocks having any size and performing any function for the integrated circuit 1 .

[0018] The integrated circuit 1 is provided with a SIST controller 28 which itself has an interface 30 . The SIST controller 28 is operative to control the signal integrity self-test function of the integrated circuit 1 and to output SIST re...

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Abstract

An integrated circuit (1) comprises a monitor (Ml, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (Ml, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SRl, SR2, SR3) and is operable to output monitor data through the shift register (SRl, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.

Description

technical field [0001] The present invention relates to an integrated circuit (IC) structure, and in particular, to a signal integrity self-test (SIST) structure. Background technique [0002] Advances in manufacturing technology have made it possible to place larger and denser circuits on a single semiconductor integrated circuit. This is especially the case if the circuits are implemented in a regular or cellular structure, such as random access memories. A major problem associated with high density devices is the testing of the devices. In order to maintain higher reliability, the device testing process needs to provide good coverage of defects that may occur in the integrated circuit. [0003] One technique for providing integrated circuit testing is the so-called SIST architecture (Signal Integrity Self-Test Architecture). The purpose of the SIST architecture is to allow real-time monitoring of important parameters characterizing the electrical characteristics of int...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185G01R31/3167
CPCG01R31/318536G01R31/3167
Inventor 马塞尔·佩尔戈姆亨德里克斯·J·M·维恩德里克
Owner NXP BV