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Common-source common-gate current mirror offset method and its bias circuit

A cascode, bias circuit technology, applied in the field of circuits, can solve problems such as small voltage space

Inactive Publication Date: 2010-04-21
苏州中科集成电路设计中心有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The cascode current mirror is a very commonly used current bias, it has the ability to resist power supply noise, make the reference voltage not affected by the power supply voltage change, reduce power consumption, and enable the circuit to work at a lower power supply voltage and other advantages, but its disadvantage is that the distributable voltage space is small, especially for power supply voltages of 1.8V or lower than 1.8V
The resulting problem is that if the usual cascode current mirror bias method is used, it is difficult to adjust all the transistors in the circuit to the saturation region, so that some transistors are in the saturation region and the other part is in the non-saturation region. ; Especially when running the corner model simulation, the existing cascode current mirror bias method makes the transistors in the saturation region under the original tt model, and some also run out of the saturation region, so the circuit designer usually spends a lot time to adjust the quiescent operating point of transistors in cascode current mirror circuits
It can be seen that the existing cascode current mirror bias method and its bias circuit need to be improved

Method used

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  • Common-source common-gate current mirror offset method and its bias circuit
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  • Common-source common-gate current mirror offset method and its bias circuit

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Experimental program
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Effect test

Embodiment 1

[0017] combine figure 1 The cascode current mirror circuit biasing method involved in the present invention is further introduced. The present invention adopts the dynamic tracking bias method to the cascode current mirror circuit. The specific way is that the p-type transistor network (also known as the PMOS network, hereinafter collectively referred to as the PMOS network) in the figure can include a p-type transistor or multiple p-type transistors. Similarly, the n-type transistor network in the figure (also referred to as NMOS network, hereinafter collectively referred to as NMOS network) may include one n-type transistor or multiple n-type transistors.

[0018] If the PMOS network 1 contains two p-type transistors, the PMOS network 2 connected to it is the output terminal, and the PMOS network 2 contains two p-type transistors; while the NMOS network 1 contains an n-type transistor, and the NMOS network 2 connected to it is the input terminal, NMOS network 2 includes an...

Embodiment 2

[0022] This embodiment provides a specific cascode current mirror bias circuit. figure 2 Is the schematic diagram of the cascode current mirror bias circuit.

[0023] P-type transistors P1, P2, P3, and P4 are four p-type transistors in a common cascode current mirror, and their sizes are 40u / 1u, 125u / 1u, 40u / 1u, 125u / 1u; n-type transistor N1 , N2 are two n-type transistors in the usual cascode current mirror, both of which have a size of 10u / 0.5u. ​​An n-type transistor N3 is inserted between the PMOS and NMOS of the cascode current mirror, and its size is 10u / 1.5u, the gate of N3 is connected to the power supply, the drain of N3 is connected to the gate of P1, and the source is connected to the gate of P2. The voltage of the drain of N3 can be adjusted to a predetermined value by adjusting the size of P1, and the voltage of the source of N3 can be obtained by adjusting the size of N3. The n-type transistor N3 plays a key role in biasing the cascode current mirror, that is...

Embodiment 3

[0025] This embodiment provides another specific cascode current mirror bias circuit. image 3 Is the schematic diagram of the cascode current mirror bias circuit.

[0026] image 3 It is another schematic diagram of cascode current mirror bias circuit. N-type transistors N4, N5, N6, and N7 are four n-type transistors in a common cascode current mirror, and their sizes are 10u / 0.5u, 50u / 0.5u, 10u / 0.5u, 50u / 0.5u; P-type transistors P5 and P6 are two p-type transistors in a common cascode current mirror, and their sizes are both 40u / 1u. A p-type transistor P7 is inserted between the PMOS network and the NMOS network of the cascode current mirror, and its size is 20u / 1.5u. The gate of P7 is grounded, and the drain of P7 is connected to the drain of the output-side transistor N5. It is also connected with the gates of N4 and N6, and the source of P7 is connected with the drain of transistor P6 and connected with the gates of N5 and N7. The p-type transistor P7 plays a very cri...

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PUM

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Abstract

The invention belongs to the circuit field, relating to a cascode current mirror biasing method and circuit, where a transistor is connected in series between n-type and p-type transistor networks inacascode current mirror circuit, the gate of this transistor is connected with power supply or grounded, the source and drain of this transistor are respectively connected to the drains of the n-typea nd p-type transistor networks, and the source and drain of this transistor are respectively used to bias the two gates of the cascode current mirror; it can make all the transistors in the cascode current mirror so that a designer need not spend very much time in regulating static operating point of the cascode current mirror.

Description

technical field [0001] The invention belongs to the field of circuits, in particular to a cascode current mirror bias method and a bias circuit thereof. Background technique [0002] The cascode current mirror is a very commonly used current bias, it has the ability to resist power supply noise, make the reference voltage not affected by the power supply voltage change, reduce power consumption, and enable the circuit to work at a lower power supply voltage and other advantages, but its disadvantage is that the distributable voltage space is small, especially for power supply voltages of 1.8V or lower than 1.8V. The resulting problem is that if the usual cascode current mirror bias method is used, it is difficult to adjust all the transistors in the circuit to the saturation region, so that some transistors are in the saturation region and the other part is in the non-saturation region. ; Especially when running the corner model simulation, the existing cascode current mirr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05F3/26
Inventor 于峰崎
Owner 苏州中科集成电路设计中心有限公司