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Method for producing auto-alignment retracting grid metal-oxide-semiconductor transistor element

A technology for automatic alignment and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc.

Active Publication Date: 2007-12-05
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Therefore, the main purpose of the present invention is to provide a method for forming a recessed gate transistor of a trench DRAM to solve the problems of the aforementioned prior art

Method used

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  • Method for producing auto-alignment retracting grid metal-oxide-semiconductor transistor element
  • Method for producing auto-alignment retracting grid metal-oxide-semiconductor transistor element
  • Method for producing auto-alignment retracting grid metal-oxide-semiconductor transistor element

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Embodiment Construction

[0031] Please refer to Fig. 1 to Fig. 16, wherein Fig. 1 depicts the top view schematic diagram of the trench capacitance layout in the memory array area of ​​the preferred embodiment of the present invention; Fig. 2 to Fig. 16 depicts the recess Schematic cross-sectional view of the fabrication method of the type gate MOS transistor element. First, as shown in FIG. 1 and FIG. 2, a plurality of trench capacitor structures 12 are formed in the semiconductor substrate 10 in the memory array region 102, wherein FIG. 2 shows I-I of the trench capacitor structures 12 in FIG. 1 respectively. 'Cross section structure and II-II' profile structure.

[0032] As shown in FIG. 2 , the trench capacitor structure 12 includes a sidewall capacitor dielectric layer 24 and a doped polysilicon layer 26 , and each trench capacitor structure 12 has a trench capping layer. 18 protruding from the main surface 11 of the semiconductor substrate 10 .

[0033] The trench capacitor structure 12 is comp...

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Abstract

The invention provides a concave grid MOS transistor making method, firstly providing a semiconductor substrate which has memory array region and a main surface formed with pad oxidation layer and pad silicon nitride layer. And it is characterized by using symmetrical sidewall spacers formed on the sidewall of the covering layer of the groove to make grid groove and self-aligned concave grid transistor.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor element, in particular to a recessed-gate metal oxide semiconductor of a trench type dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM). (Metal-Oxide-Semiconductor, abbreviated as MOS) transistor element manufacturing method. Background technique [0002] As the size of device designs continues to shrink, the short channel effect caused by the shortening of the gate channel length of transistors has become an obstacle to further increase the integration level of semiconductor devices. In the past, methods to avoid the short channel effect have been proposed, such as reducing the thickness of the gate oxide layer or increasing the doping concentration, etc. However, these methods may simultaneously cause a decrease in device reliability or a slowdown in data transmission speed And other problems, it is not suitable for practical application in techn...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8242H01L21/336H01L21/28H10B12/00
Inventor 李友弼林瑄智何家铭
Owner NAN YA TECH