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Semiconductor device and method for manufacturing same

A semiconductor and device technology, applied in the field of semiconductor devices and their manufacturing, can solve problems such as no effective countermeasures, uncoordinated operation time, and increased threshold voltage

Pending Publication Date: 2007-12-05
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Specifically, the gist of this phenomenon is that NBTI occurs considerably in p-type MOSFETs, and when a negative bias voltage is applied to the gate electrode in a high-temperature environment, positive fixed charges are generated in the gate insulating film, resulting in increased large threshold voltage
As a result, the operating speed of the MOSFET decreases with the lapse of time, so that the operating timing of multiple MOSFETs in the semiconductor device is not coordinated, resulting in the occurrence of erroneous operation
Although NBTI has been explored and studied in consideration of various aspects, the current situation is that there is no effective countermeasure

Method used

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  • Semiconductor device and method for manufacturing same
  • Semiconductor device and method for manufacturing same
  • Semiconductor device and method for manufacturing same

Examples

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no. 1 example

[0030] FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a silicon substrate 101 and a p-type MOSFET 103 provided on the silicon substrate 101 . The p-type MOSFET 103 in this embodiment is a transistor with a surface channel structure. Also, the surrounding portion of p-type MOSFET 103 is provided with element isolation region 102 .

[0031] In p-type MOSFET 103, a pair of impurity diffusion regions 110 are provided in N-well 104 provided in silicon substrate 101 and having n-type conductivity, and channel region 105 is formed in these impurity diffusion regions between. Impurity diffusion region 110 is a diffusion layer doped with p-type impurities in the surface of n-well 104 . One will be the source region and the other will be the drain region. Also, an extension region 140 is provided in the n-well 104 .

[0032] SiO used as gate...

no. 2 example

[0075] The structure of the semiconductor device according to the present embodiment is generally similar to that of the semiconductor device 100 of the first embodiment, except that a metal layer including at least one of Hf and Zr is included in the gate insulating film, and starts from the side of the semiconductor substrate , comprising a multilayer structure of a first gate insulating film, an Hf layer, a second gate insulating film and a gate electrode. In this embodiment, description will focus on points different from the first embodiment.

[0076] FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor device 200 according to the present embodiment.

[0077] The semiconductor device 200 includes a silicon substrate 101 and a p-type MOSFET 203 provided on the silicon substrate 101 . Also, the surrounding portion of p-type MOSFET 203 is provided with element isolation region 102 . In p-type MOSFET 203, a pair of impurity diffusion re...

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Abstract

The semiconductor device includes a silicon substrate, an SiO2 film provided so as to be in contact with the upper portion of the silicon substrate, and a p-type MOSFET including a polycrystalline silicon film, which is provided so as to be in contact with the upper portion of the SiO2 film. Further, an interior of the SiO2 film or an interface of the SiO2 film with the polycrystalline silicon film is provided with a region containing at least one metallic element of Hf and Zr at an area density of not higher than 1.3x10<14 >atoms / cm<2>.

Description

[0001] This application is based on Japanese Patent Application No. 2006-148,381, the contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to a semiconductor device including a metal oxide semiconductor field effect transistor (MOSFET) and a method of manufacturing the same. Background technique [0003] Due to the remarkable miniaturization of semiconductor devices in recent years, various innovations are required in order to ensure the performance and reliability of MOSFETs. Under such circumstances, in order to obtain improved performance of MOSFETs, research is actively being conducted on the use of a so-called high-k film having a high dielectric constant as a gate insulating film. Typical high-k materials include oxides of elements such as zirconium (Zr), hafnium (Hf), and others. Even if the physical thickness of the gate insulating film is increased to some extent, the use of this material for the gate insula...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/51H01L21/336H01L21/28
CPCH01L29/4958H01L21/28079
Inventor 君塚直彦中原宁
Owner NEC ELECTRONICS CORP