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Method and system for debugging multithreading procedure in a multicore architecture

A threading and debugger technology used in the field of debugging multithreaded programs and systems executed in a multicore architecture

Active Publication Date: 2012-03-14
斯诺普西斯公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the past, applications for multi-core architectures were written on a custom basis, resulting in poorly portable hardware-specific applications
Also, the debugging of these apps is very specific

Method used

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  • Method and system for debugging multithreading procedure in a multicore architecture
  • Method and system for debugging multithreading procedure in a multicore architecture
  • Method and system for debugging multithreading procedure in a multicore architecture

Examples

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Embodiment Construction

[0036] figure 1 A logical view of the system framework showing an example of a typical multi-core processor architecture. The framework includes a plurality of processing resources 150, each of which may or may not be similar to other processing resources 150 in the multi-core architecture. The processing resource 150 may be any form of hardware or its equivalent capable of executing instructions, and thus may include a general-purpose processing resource 150, or a processing resource 150 with an effectively restricted instruction set, such as an input-output device.

[0037] The system framework also includes a centralized thread management and allocation system comprising a thread management and allocation controller 130 and a dedicated tightly coupled memory 190 connected to the controller via a memory interface 180 . Each processing resource 150 can access controller 130 through interconnect 115 . should understand, figure 1 The implementation of the architecture does...

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PUM

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Abstract

The invention provides a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of multiple parameters relating to the function and / or identity and / or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

Description

technical field [0001] The invention relates to a method and device for debugging in a multi-core architecture. Background technique [0002] In recent years, in order to make silicon efficiency (i.e., "application achievable" MIP / mm 2 or MIP / mW), there is a tendency to manufacture processors that contain multiple cores. This multi-core architecture is ideally suited for running thread-based applications because a thread defines an autonomous work package containing execution state, instruction flow, and data groups, which by definition can execute in parallel with other threads. However, this parallel execution introduces additional problems to the software debugging process used on these multi-core architectures. Software debugging is a general term for locating and correcting errors in the execution of computer applications. [0003] One of the key problems facing software debugging is the Heisenberg bug (also known as the "probe effect"). Any code added for debuggin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
CPCG06F11/3636G06F11/30G06F11/36
Inventor 马克·大卫·李佩特阿耶温·翁
Owner 斯诺普西斯公司