Circuit for calculating energy of orthogonal signal

Abstract

In this circuit, the absolute value unit is used for getting |I|, the absolute value of the orthogonal signal I, and |Q|, the absolute value of the orthogonal signal Q. The right-shifting unit moves |I| to the right by 1 digit to get |I|/2 and moves |Q| to the right by 1 digit to get |Q|/2. The first adder adds the |I|/2 to the |Q| to get |I| /2+|Q|. The second adder adds |Q|/2 to the |I| to get |Q|/2+|I|. The comparator compares the absolute value |I| with the absolute value |Q|. According to the comparison result, the comparator controls the selector to select |Q|/2+|I| or |I|/2+|Q| as output energy value.

Description

technical field [0001] The invention relates to the field of energy calculation, in particular to an orthogonal signal energy calculation circuit. Background technique [0002] The calculation of signal energy is an important research direction in modern communication. The calculation result of signal energy will affect the execution of many subsequent algorithms. For example, in Automatic Gain Control (AGC), it is necessary to obtain the energy of the input signal, and then adjust the amplitude of the input signal according to its energy. , so that the energy of the signal actually received by the subsequent circuit can converge within a certain range, so as to facilitate calculation or reception. Among them, the orthogonal signal is a commonly used method in communication, and the mutually orthogonal signals interfere with each other the least, and contain a large amount of information. [0003] In an analog system, square detection is usually used for signal energy calc...

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Problems solved by technology

However, for hardware circuits, it is very difficult to perform the square root operation

[0006] There are some methods in the prior art that can further simplify the calculation of signal energy, such as assuming a set of orthogonal signals I, Q, using |I|+|Q| to approximate The specific hardware circuit diagram is shown in Figure 2. Let I and Q be n-bit signed fixed-point numbers, where I[n-1] and Q[n-1] are I[n-1:0] and Q[ The sign bit of n-1:0], the operation result is only n+1 bits, and it is easy to implement on the circuit, and the resources used are very few, but the operation result is the same as There is still a large gap in the accuracy of the calculated results

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