AHB interconnection matrix interface

An interface and matrix technology, applied in the field of AHB interconnection matrix interface, can solve the problems of infeasibility and difficulty in increasing the frequency of the bus system, so as to achieve the effect of increasing the operation efficiency of the matrix and improving the overall operation efficiency

Inactive Publication Date: 2008-03-12
ZTE CORP
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  • Abstract
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  • Application Information

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Problems solved by technology

The proposal of this structure realizes the parallel operation of the AHB bus and improves the efficiency of the bus. However, in practical applications, it is found that this solution is not feasible because the hready signal is a global signal, and when the AHB bus is connected to multiple After the first AHB master device and slave device, the hready of all these devices are actually connected together, and the hready is even connected to every register, which leads to the biggest problem of this scheme. The frequency of this bus system is difficult to increase.

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Embodiment Construction

[0021] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0022] The AHB bus is a high-speed bus used by many embedded processor (especially ARM CPU) systems for data transmission. This interface design uses multiple AHB master devices to reach the AHB through a streamlined matrix with a cache. From the device side, high-speed, high-efficiency, parallel operation between buses is realized.

[0023] Aiming at the memory system, the present invention adds an N-way cache to this type of AHB matrix under the condition that the consistency of data is guaranteed at each interface, so that the efficiency of the AHB interface can be greatly improved. Such a matrix may be used as a cache memory for the operating system.

[0024] F...

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Abstract

The present invention discloses an AHB interconnection matrix interface, which comprises a main device control module, which is used to receive the information from the main device and to latch the information, and to send an application for a request arbitration module in a pipeline way; the request arbitration module, which is used to arbitrate the application sent by the main device control module, and to generate the arbitration information; and a sub-device control module, which is used to get the arbitration information from the request arbitration module, and the internal cache or the sub-device performs an information interaction with the main device control module according to the content of the arbitration information and the information. Through the present invention, the pipeline and a high-speed buffer are added on the interconnection matrix through the AHB interconnection matrix with the high-speed buffer, to enable the operating efficiency of the matrix to be increased greatly, simultaneously, due to the high-speed buffer being taken as a sharing high-speed buffer, the integrated operating efficiency of a multi-kernel system can be improved.

Description

technical field [0001] The invention relates to a high-speed bus AHB bus of the AMBA protocol, in particular to an AHB interconnection matrix interface. Background technique [0002] The AHB interconnection matrix is ​​a system bus connection structure proposed by ARM, as shown in Figure 1. The AHB interconnection matrix proposed by ARM includes the following parts: input latch part (INPUT STAGE), decoding part (DECODEC), channel selection part (MUX). The proposal of this structure realizes the parallel operation of the AHB bus and improves the efficiency of the bus. However, in practical applications, it is found that this solution is not feasible because the hready signal is a global signal, and when the AHB bus is connected to multiple After the first AHB master device and slave device, the hready of all these devices are actually connected together, and the hready is even connected to every register, which leads to the biggest problem of this scheme. The frequency of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/10H04L12/56G06F13/40G06F13/42
Inventor 陈家锦
Owner ZTE CORP
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