Processor

A processor and buffer technology, applied in the field of processors, can solve the problems of difficulty in fully storing and providing instructions, complicated switching of instruction buffer control, and shortening of time, so as to avoid waiting for access, low power consumption, and reduce frequency. Effect

CN101156134AInactive Publication Date: 2008-04-02PANASONIC CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2008-04-02
Estimated Expiration
Not applicable · inactive patent

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Abstract

A processor (100) includes an ordinary instruction buffer (122) for storing and supplying one or more instructions fetched from an instruction cache (10), a TAR instruction buffer (123) for storing the one or more instructions fetched from the instruction cache (10) and supplying them secondarily, a selector (121) for seiecting either the ordinary instruction buffer (122) or the TAR instruction buffer (123) as an instruction supplying source, and an instruction fetch control unit (102) for fetching, when a TAR filling instruction is executed, one or more instructions specified by the TAR filling instruction, and for controlling the selector (121) to select the TAR instruction buffer (123), in the case where case one or more fetched instructions are repeatedly supplied, thereby to supply an instruction through the selector (121) from the TAR instruction buffer (123).
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Description

technical field

[0001] The present invention relates to processors and the like that fetch and execute instructions stored in an instruction cache, and more particularly, to a processor capable of executing instructions in a loop portion without accessing the instruction cache. Provide instructions. Background technique

[0002] In recent years, digital home appliances such as mobile phones, digital video cameras, and digital video recorders have become more and more popular. And, for processors mounted in these products, processors with low power consumption and high processing capability are required.

[0003] In this regard, for example, a processor has been proposed that achieves low power consumption and high processing capability by shortening penalty cycles due to branch prediction errors (see, for example, Non-Patent Document 1).

[0004] Specifically, generally, the processor includes two instruction buffers in the part that manages instruction fetching, and any o...

Examples

Embodiment 1

[0049] Hereinafter, Embodiment 1 according to the present invention will be described with reference to the drawings.

[0050] The processor of this embodiment is characterized in that, in addition to the instruction buffer for storing general instructions, it also includes an instruction buffer for storing the instructions of the loop part. The instruction buffer provides instructions instead of repeatedly fetching them from the instruction cache.

[0051] Further, this feature is that, in addition to including these instruction buffers, it also includes an instruction buffer for storing the instructions of the return part of the subroutine. The buffer provides instructions.

[0052] The processor of this embodiment is explained based on the above.

[0053] First, the configuration of the processor of this embodiment will be described.

[0054] As shown in FIG. 1 , the processor 100 includes, in addition to a general instruction buffer 122 storing general instructions, an ...

Embodiment 2

[0129] Next, Embodiment 2 according to the present invention will be described with reference to the drawings.

[0130] The processor of this embodiment is characterized in that it includes a plurality of instruction buffers for storing instructions of loop parts, and provides a plurality of instructions of loop parts.

[0131] The processor of this embodiment is explained based on the above.

[0132] In addition, the same reference numerals are assigned to the same structural parts as those of the first embodiment, and description thereof will be omitted.

[0133] First, the structure of the processor of the embodiment will be described.

[0134] As shown in FIG. 10 , the differences between the processor 200 and the processor 100 are the following (1) to (7).

[0135] (1) The command acquisition control unit 202 is included instead of the command acquisition control unit 102 .

[0136] If the instruction execution unit 101 executes the first filling instruction for TAR, t...