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Method of forming lithographic and sub-lithographic dimensioned structures

A size and lithography technology, applied in the direction of microlithography exposure equipment, optics, optomechanical equipment, etc., can solve the problems that other structures cannot, the pace of minimum feature size reduction slows down, etc.

Inactive Publication Date: 2008-04-16
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this minimum feature size has been and continues to be reduced by using shorter wavelength exposure irradiance and increasing the effective numerical aperture, the pace of this minimum feature size reduction has begun to slow
Also, while some structures benefit ICs from being smaller, others do not.

Method used

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  • Method of forming lithographic and sub-lithographic dimensioned structures
  • Method of forming lithographic and sub-lithographic dimensioned structures
  • Method of forming lithographic and sub-lithographic dimensioned structures

Examples

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Embodiment Construction

[0009] Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are top views, and Figures 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are views through their respective Figures 1A , 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A of the respective lines 1B-1B, 2B-2B, 3B-3B, 4B-4B, 5B-5B, 6B-6B, 7B-7B, 8B-8B, 9B-9B and 10B-10B are cross-sectional views, and Figures 8C and 9C are cross-sectional views through respective lines 8C-8C and 9C-9C of Figures 8A and 9A respectively, which illustrate the fabrication of The steps of the structure of the embodiment;

[0010] In FIGS. 1A and 1B , a core layer 105 is formed on the top surface of a base layer 100 . The base layer 100 is in one example an interlayer dielectric layer (ILD) itself formed on a semiconductor substrate (not shown). Photoresist regions 110A and 110B are formed on the top surface of the core layer 105 . By applying a photoresist layer to the top surface of the core layer, exposing the photoresist layer to actinic radiation th...

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Abstract

A method of forming lithographic and sub-lithographic dimensioned structures. The method includes forming a mandrel layer on a top surface of an underlying layer and then forming a masking layer on a top surface of the mandrel layer; patterning the masking layer into a pattern of islands; transferring the pattern of islands into the mandrel layer to form mandrel islands, the top surface of the underlying layer exposed in spaces between the mandrel islands; forming first spacers on sidewalls of the mandrel islands; removing the mandrel islands, the top surface of the underlying layer exposed in spaces between the first spacers; forming second spacers on sidewalls of the first spacers; and removing the first spacers, the top surface of the underlying layer exposed in spaces between the second spacers.

Description

technical field [0001] The present invention relates to the field of integrated circuit fabrication, and more particularly to methods for forming lithographic and sublithographic structures. Background technique [0002] As the performance of integrated circuits increases and the size of integrated circuits decreases, the size of the structures making up the integrated circuits also decreases. These structures are defined photolithographically, and there is a minimum feature size that can be defined by the photolithographic process. Although the minimum feature size has been and continues to be reduced by using shorter wavelength exposure radiation and increasing the effective numerical aperture, the pace of this minimum feature size reduction has begun to slow. At the same time, while some structures benefit integrated circuits from being smaller, others do not. Also, for some structures it is better that they have dimensions smaller than the lithographic minimum feature ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20G03F7/00H01L21/027
CPCH01L21/76816H01L21/31144H01L21/0337H01L21/0338
Inventor C·W·科布格尔三世D·V·霍拉克古川俊治
Owner IBM CORP
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