Method for forming semiconductor device and semiconductor device

Abstract

The invention discloses a forming method of a semiconductor device and comprises the following steps: a substrate is provided; a gate oxide layer is formed on the substrate; a poly silicon layer is formed on the gate oxide layer; the poly silicon layer and the gate oxide layer are etched to form gates; a strained layer with compressive stress is deposited on the substrate and the gates; the strained layer is removed. A semiconductor device made by the manufacturing method of the invention has the advantages that the substrate surface on both sides of the gate is not lower than the substrate surface below the gate, which relieves the depression conditions of source sections or leakage sections and solves the problem of the degradation of the device caused by the depression conditions.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device and the semiconductor device. Background technique [0002] With the rapid development of ultra-large-scale integrated circuits, the integration of chips is getting higher and higher, and the size of devices is getting smaller and smaller. The impact of various effects caused by the high density and small size of devices on the production results of semiconductor processes is also becoming more and more prominent. . [0003] In metal-oxide-semiconductor field-effect transistors (MOSFETs), when the device size is reduced to below 65nm, some unevenness on the wafer surface, such as the depression on the source / drain surface, will have a significant impact on the performance and working speed of the device , and the MOSFET device manufactured by the existing manufacturing process often has depressions on the wafer surf...

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Problems solved by technology

like Figure 1E As shown, since the recesses 110 and 120 on both sides of the gate and its sidewall layer are located at the substrate where the source / drain is located, the source / drain 107, 108 formed by ion implantation at this position, and the above The metal silicide 130 must also be recessed with the substrate surface, so that the source / drain region and the channel under the gate are not on the same level, which is detrimental to the performance of the device

[0006] Especially for small-sized devices, because the distance between the source / drain is smaller, it is more sensitive to the depression of the source / drain silicon surface on both sides of the gate, the above-mentioned substrate surface on both sides of the gate The recesses 110 and 120 make the source / drain of the device lower than the channel below the gate, which will lead to multiple performance parameters of small-sized devices, such as parasitic capacitance between the gate and source / drain, the source of the device / drain region resistance, device drive current, device operating speed, etc., have significant changes, and eventually lead to a decline in the overall performance of the device

[0007] In order to fill the depressions that appear on the wafer surface during the manufacturing process, the Chinese patent application No. 97199089.1 discloses a method for filling the depressions on the wafer surface, but the method utilizes tetraethyl orthosilicate (TEOS) to grow silicon oxide. The flattening of the wafer surface, and it is applicable to the wafer surface with silicon oxide on the surface, this method obviously cannot be used to make up for the depression of the substrate surface at the source / drain position mentioned above

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