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Multi-chip packaging structure and making method thereof

A technology of multi-chip packaging and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc. In order to simplify the circuit layout and reduce the overall thickness and size

Active Publication Date: 2008-08-27
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the overall thickness and size of the above-mentioned multi-chip packaging structure 100 are not easy to shrink, which no

Method used

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  • Multi-chip packaging structure and making method thereof
  • Multi-chip packaging structure and making method thereof
  • Multi-chip packaging structure and making method thereof

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Experimental program
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Embodiment Construction

[0076] 2A to 2G are schematic diagrams of the front-end process of the manufacturing method of the multi-chip packaging structure according to an embodiment of the present invention. In the previous stage of the process, it is mainly performed on the first silicon wafer 200 , please refer to the embodiment of FIG. 2A and FIG. 2B first. Firstly, the first step is to provide the first silicon wafer 200 with IC layout and fabrication completed. The first silicon wafer 200 has an active surface 202 and an opposite back surface 204 . A plurality of pads 206 are disposed on the active surface 202 and can be exposed in a passivation layer 208 covering the active surface 202 . Next, the second step is to attach a first metal layer 210 and a substrate 220 on the back surface 204 of the first silicon wafer 200 . The first metal layer 210 is located between the first silicon chip 200 and the substrate 220 . The first metal layer 210 is adhered to the back surface 204 of the first sili...

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Abstract

The invention relates to a manufacturing method for a multichip packaging structure, wherein, firstly, a plurality of concave cavities which are generated by local removal of a first silicon slice and a first metallic layer are formed on a predetermined cut line of the first silicon slice, and a conductive wall of a first line layer is electrically connected with a cutting profile of the first metallic layer which is exposed into the concave cavities; moreover, a second silicon slice and a conductive lug of the second silicon slice are pressed into a cover layer and electrically connected with the first line layer; secondly, the first metallic layer is patterned so as to form a second line layer which is provided with a plurality of second welded gaskets; thirdly, the first silicon slice and the second silicon slice are cut along the predetermined cut line so as to form a plurality of separated multichip packaging structures.

Description

technical field [0001] The invention relates to a semiconductor packaging process, and in particular to a manufacturing method of a multi-chip packaging structure. Background technique [0002] With the advancement of semiconductor technology, Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip package (F / C package) and multi- Chip module (Multi-Chip Module, MCM) and other high-density integrated circuit packaging technologies have also emerged. For high-density integrated circuit packaging, shortening the length of the connecting lines will help to increase the speed of signal transmission, so the application of bumps has gradually become the mainstream of high-density packaging. [0003] FIG. 1 is a schematic cross-sectional view of a multi-chip packaging structure in the prior art. Please refer to FIG. 1 , the multi-chip packaging structure 100 is composed of a carrier 110 , a first chip 120 , a second chip 130 , a plurality of bonding wires 140 and an encapsulan...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/60H01L21/78H01L25/00H01L25/065H01L23/488H01L23/482
CPCH01L2924/3025H01L2224/16225H01L2224/48227H01L2924/15311H01L2224/73265H01L2224/32145H01L24/19H01L2224/48465H01L2924/14H01L2924/18162H01L2224/12105H01L2224/16145H01L2224/92244H01L2224/94H01L2224/19H01L2224/73267H01L2224/73253H01L21/568H01L2224/04105H01L2224/32245H01L2924/00H01L2924/00012H01L2224/81
Inventor 王建皓
Owner ADVANCED SEMICON ENG INC