Data processing method and communications system and relevant equipment

Abstract

The embodiment of the invention discloses a data processing method, a communication system and relevant equipment. The invention is used to realize the DMA access of IO equipment on the basis of multi-CPU. The method of the embodiment comprises the following steps that: a direct memory access DMA command is received, wherein, the DMA command comprises a DMA address of a memory for indicating the DMA operation access; according to the DMA command, a DMA address indicated by an address space of a receiver is acquired; according to the acquired DMA address indicated by the address space of the receiver, the memory is accessed. The embodiment of the invention also discloses the communication system and the relevant equipment. The embodiment of the invention can realize the DMA access of the IO equipment on the basis of the multi-CPU.

Description

Data processing method, communication system and related equipment technical field The invention relates to the field of communication, in particular to a data processing method, a communication system and related equipment. Background technique The central processing unit (CPU, Center Processing Unit) communicates with the input-output (IO, Input-Output) device through a peripheral device expansion interface (PCIE, Peripheral Component Interconnect Express) bus, and the main addressing mode of PCIE is based on address addressing. If there are two or more processors in the PCIE bus, the address spaces between these processors may overlap. At this time, if the PCIE bus is still addressed according to the original address, it will inevitably cause address conflicts. For the above problems, the prior art proposes a solution: when there are multiple processors in the PCIE bus, use a non-transparent bridge (NTB, Non-TransparentBridge) to isolate, and the non-transparent bridge...

AI Technical Summary

Problems solved by technology

However, in the NTB system architecture of the prior art, the devices on both sides of the NTB have independent addressing spaces, and the addressing spaces on both sides may overlap. After the IO device issues a DMA command for the second IO device to access the first memory, since the DMA address information carried in the DMA command is for the addressing space of the first CPU side, when the second IO device on the other side of the NTB After the device receives the DMA command, it will access the second memory in the address space of the local side according to the DMA address information, instead of accessing the first memory on the first CPU side. Therefore, in the existing NTB system, the IO device cannot use multiple DMA command issued by CPU for DMA access

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