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Layout design method of static electricity discharge protection device and MOS device

A technology for electrostatic discharge protection and MOS devices, which is used in the manufacture of electrical components, semiconductor devices, and semiconductor/solid-state devices. degree of damage reduction

Active Publication Date: 2011-07-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The problem solved by the present invention is that the MOS device formed by the layout design method of the existing electrostatic discharge protection device cannot be opened evenly when encountering electrostatic discharge, so that the internal circuit cannot be effectively protected

Method used

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  • Layout design method of static electricity discharge protection device and MOS device
  • Layout design method of static electricity discharge protection device and MOS device
  • Layout design method of static electricity discharge protection device and MOS device

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Embodiment Construction

[0022] The invention adopts a new layout design for the MOS device applied to electrostatic discharge protection, so that the gate is grid-like, increases the current path during electrostatic discharge, and improves the electrostatic discharge tolerance of the MOS device.

[0023] Taking an NMOS device with a channel width of 360um as an example, the layout design of the present invention and the MOS device formed according to the layout design will be described in detail below.

[0024] The method of the layout design of the embodiment of the present invention is as follows:

[0025] refer to Figure 3A As shown, the first layer representing the p-type deep well 400 located in the p-type substrate is provided, and the p-type deep well 400 is exactly the p-well formed in the production process of the NMOS device;

[0026] refer to Figure 3B As shown, a second layer representing the n-type active region 600 is provided within the area surrounded by the first layer represent...

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PUM

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Abstract

The invention discloses a layout design method for a static discharging protective apparatus which includes a first layer representing a depression in an underlay; a second layer representing an active area in the area surrounded by the first layer; a third layer representing a grid in the area surrounded by the second layer and the third layer forms a gridding framework shape; a fourth layer which is arranged in the overlapped area of the gridding of the third layer and the second layer and represents a contact hole; a fifth layer which is arranged in the area surrounded by the first layer, connected with the third layer and represents metals; a sixth layer which is arranged in the area surrounded by the fifth layer and represents the communication hole of the metals and the grid. An MOSapparatus in the static discharging protective circuit formed by the layout design method of the invention has more circuit paths and can improve the static discharging tolerance of the MOS apparatus, thus more effectively protecting an inside circuit.

Description

technical field [0001] The invention relates to a layout design method of an electrostatic discharge protection device and a MOS device. Background technique [0002] In the field of chip manufacturing and application, electrostatic discharge is one of the common causes of chip failure. When the charge stored on the machine or human body contacts the chip or discharges due to electrostatic induction, electrostatic discharge occurs. At present, as the minimum feature size of semiconductor devices is getting smaller and smaller, the problems caused by electrostatic discharge will become more and more serious. Usually, for the protection of the electrostatic discharge of the device, most of them are considered from the circuit design. [0003] The invention of Chinese Patent No. 01125832.2 discloses an electrostatic discharge protection circuit, comprising: a resistance element, one end of which is electrically connected to a voltage source; a capacitance element, one end of w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/336H01L21/28H01L27/088H01L29/78H01L29/423G06F17/50
Inventor 廖金昌张莉菲
Owner SEMICON MFG INT (SHANGHAI) CORP
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