Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Wafer level semiconductor package with dual side build-up layers and method thereof

A semiconductor, wafer-level technology, applied in the field of wafer-level packaging structure, can solve problems such as cost increase

Inactive Publication Date: 2008-12-17
ADVANCED CHIP ENG TECH INC
View PDF1 Cites 33 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The cost of the process thus increases

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Wafer level semiconductor package with dual side build-up layers and method thereof
  • Wafer level semiconductor package with dual side build-up layers and method thereof
  • Wafer level semiconductor package with dual side build-up layers and method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0046] The present invention will be described in detail below with its preferred embodiments and accompanying drawings. It should be understood that all the preferred embodiments in the present invention are for illustration only, not for limitation. Therefore, except for the preferred embodiment herein, the present invention can also be widely applied in other embodiments. And the present invention is not limited to any embodiment, and should be determined by the scope of the attached patent application and its equivalent fields.

[0047] The present invention discloses a fan-out (or diffused) wafer-level packaging structure, using a substrate 102 which has a predetermined first terminal contact conductive pad 104 formed thereon, and pre-formed in the substrate 102 accommodating through-die holes 106 that will penetrate from the upper surface of the substrate to the lower surface of the substrate. At least one die with metal pads is disposed in the die-accommodating throug...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention discloses a structure of package comprising a substrate with at least one die receiving through holes, a conductive connecting through holes structure and a contact pads on both side of substrate. At least one die is disposed within the die receiving through holes. A first material is formed under the die and second material is formed filled in the gap between the die and sidewall of the die receiving though holes. Dielectric layers are formed on the surface of both side of the die and the substrate. Redistribution layers (RDL) are formed on the both sides and coupled to the contact pads. A protection bases are formed over the RDLs.

Description

【Technical field】 [0001] The present invention relates to wafer-level packaging (WLP) structures, and more particularly to fan-out WLPs with double-sided build-up layers covered to improve reliability and reduce device size. 【Background technique】 [0002] In the field of semiconductor components, the density of the components is continuously increasing, while the size is gradually shrinking. The demand for packaging or interconnecting technology applied to high-density components is also increasing to meet the above-mentioned conditions. In a general flip-chip attachment method, an array of tin bumps is formed on the surface of the die. The composition of the tin bumps can use tin compound materials to produce desired tin bump patterns through a solder mask. The functions of chip packaging include power distribution, signal distribution, heat dissipation, protection and support, etc. As semiconductor technology becomes more complex, traditional packaging technologies, su...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/48H01L23/538H01L21/60
CPCH01L23/49816H01L23/5389H01L24/82H01L2924/01013H01L2924/01015H01L2924/01029H01L2924/01059H01L2924/01075H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/09701H01L2924/14H01L2924/15311H01L2924/19043H01L2924/01005H01L2924/01006H01L2924/01033H01L2924/014H01L2924/10253H01L24/97H01L2224/24227H01L2924/351H01L2924/181H01L2924/3511H01L2224/04105H01L2224/12105H01L24/24H01L2924/00H01L2224/18H01L24/18
Inventor 杨文焜
Owner ADVANCED CHIP ENG TECH INC
Features
  • Generate Ideas
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com