Wafer-class encapsulation structure and preparation method thereof

Abstract

The invention relates to a wafer-level packaging structure which comprises a chip, a plurality of ball bottom metal layers and a plurality of polymer projections. The chip is provided with a plurality of welding pads and a protection layer, wherein the protection layer is provided with a plurality of first openings to expose the welding pads. The ball bottom layer covers the exposed welding pads by the protection layer. The polymer projections is configured on the ball bottom metal layer. Each polymer projection comprises a polymer layer, at least a conductive pillar and a junction layer. The polymer layer is provided with at least a through hole. The conductive pillar is configured in the through hole and the junction layer covers the conductive pillar. The polymer layer is electrically connected with the corresponding welding pads through the conductive pillar. The polymer layer is higher than the conductive pillar, and the junction layer above the conductive pillar is provided with a depression. According to the invention, the reliability of the electric connection between a chip package body and a carrier plate can be improved.

Description

Technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof, and more particularly to a wafer-level packaging structure and a manufacturing method thereof. Background technique [0002] In recent years, as the growth of portable electronic products, handheld communications and consumer electronic products has surpassed that of traditional personal computer (PC) products, electronic components have continued to move towards high-capacity, narrow-line width High-density, high frequency, low energy consumption, and multi-functional integration are developing. In terms of integrated circuit (IC) packaging technology, in order to meet the requirements of high input / output (I / O), high heat dissipation and reduced package size, chip scale package (CSP) The demand for high-end packaging technologies such as wafer level package is increasing. [0003] Different from the traditional packaging technology that uses a single die as a processing tar...

AI Technical Summary

Problems solved by technology

However, the elasticity of the metal bump is poor. When the electrical connection between the bump and the pad is under stress, the metal bump cannot be used as a buffer, so the electrical connection between the bump and the pad is easily damaged.

In this way, the reliability of the electrical connection between the bump and the pad will be reduced, thereby reducing the reliability of the electrical connection between the chip package and the carrier.

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