Method for forming micropatterns in semiconductor device

Abstract

A method for forming micropatterns in a semiconductor device includes forming a first etch stop layer over a etch target layer, forming a second etch stop layer over the first etch stop layer, forminga first sacrificial layer over the second etch stop layer, etching portions of the first sacrificial layer and second etch stop layer to form first sacrificial patterns, forming an insulation layer along an upper surface of the first etch stop layer, forming a second sacrificial layer over the insulation layer to cover the insulation layer, planarizing the second sacrificial layer and the insulation layer to expose the first sacrificial patterns, removing the first sacrificial patterns and the second sacrificial layer, etching the second etch stop layer and insulation layer to thereby form second sacrificial patterns, etching the first etch stop layer, and etching the etch target layer.

Description

[0001] related application [0002] This application claims priority from Korean Patent Application No. 2007-0092642 filed on September 12, 2007, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates to methods of fabricating micropatterns in semiconductor devices. Background technique [0004] Recently, as semiconductors become highly integrated, lines and spaces (LS) below 40 nm are required. However, typical exposure equipment cannot form LSs below 60 nm. Therefore, a double patterning technique (DPT) has been introduced to form fine LSs below 60 nm using typical exposure equipment. [0005] Figures 1A to 1D A cross-sectional view illustrating a method of forming a typical micropattern by a DPT process is illustrated. refer to Figure 1A , forming an etching target layer 101 on the substrate 100 . First and second hard masks 102, 103 are sequentially formed on the resulting structure. [0006] A ph...

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