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Solid disc storage system and solid disc controller of paralleling data access architecture

A memory controller and storage system technology, applied in the direction of input/output to record carrier, etc., can solve the problems of unable to reach flash memory, unable to connect flash memory module, unable to achieve expansion, etc.

Active Publication Date: 2009-04-01
PHISON ELECTRONICS
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  • Summary
  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, such an architecture mainly concentrates operations such as access control, data, and even optimization required by the flash memory modules on the central microprocessor of the host computer 280 for processing, so it must occupy The central microprocessor resources of the host 280 will make the efficiency of the host 280 worse
[0008] In addition, because the shared bus (Shared Bus) 260 is used, it will not be possible to connect to too many flash memory modules, so the purpose of expansion will not be achieved
Such an architecture obviously fails to achieve the purpose of using flash memory to replace hard disk storage devices

Method used

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  • Solid disc storage system and solid disc controller of paralleling data access architecture
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  • Solid disc storage system and solid disc controller of paralleling data access architecture

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Embodiment Construction

[0065] The present invention proposes a solid state disk (SSD) storage system with a parallel data access architecture. The solid state disk (SSD) storage system uses flash memory as a storage medium. The solid-state disk (SSD) storage system proposed by the present invention includes a solid-state disk (SSD) controller and a plurality of transmission interfaces with predetermined bits and bandwidths, and the SSD controller communicates with one or more transmission interfaces via each transmission interface. The flash memory constitutes a channel for transmitting control signals and data. That is, an independent transmission channel is formed between the SSD controller, the transmission interface with multiple bits, and the flash memory.

[0066] The solid-state disk (SSD) storage system proposed by the present invention constructs a plurality of parallel transmission channels between the SSD controller, the transmission interface, the control interface, and the flash memory...

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Abstract

The invention proposes a solid state disk (SSD) memory system provided with a parallel data access framework and a solid disk controller; wherein, the solid state disk (SSD) controller is connected with a plurality of transmission interfaces which are provided with prior decided bits and bandwidths. The SSD controller forms a channel for transmitting a control signal and data through each transmission interface and one or a plurality of flash memories. In other words, an independent transmission channel is formed between the SSD controller and the transmission interfaces provided with a plurality of bits and the flash memories. In an embodiment, the transmission interfaces are the transport protocols above MMC 4.0. Besides, a host computer carries out control and access on the flash memories through an SATA bus interface and the SSD controller; a DMA engine provided with a bidirectional connection interface in the SSD controller is utilized for transmitting data.

Description

technical field [0001] The present invention relates to a solid state disk (SSD) storage system, and in particular to a solid state disk (SSD) storage system and a solid state disk controller with parallel data access architecture. Background technique [0002] Due to the continuous improvement of data transmission technology of high-speed serial port (Serial Port) and parallel port (Parallel Port) in recent years, high-speed interface devices such as Universal Serial Bus (USB) 2.0, IEEE1 394, IDE Ultra DMA Mode, etc. have been developed. Come out, let the data transmission speed increase greatly. Unfortunately, the data transmission speed of flash memory (Flash Memory) type storage elements has not increased accordingly, and is much lower than the data transmission speed of high-speed serial ports and parallel ports. Taking a high-speed serial port such as USB 2.0 or IEEE1 394 as an example, the defined data transmission rates are 480 Mbps and 800 Mbps, respectively. The ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
Inventor 潘健成李建龙
Owner PHISON ELECTRONICS