Transceiver system with reduced latency uncertainty, programmable logic device comprising transceiver system, data system and method of transmitting and receiving data

Abstract

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Provisional Application No. 61, filed December 21, 2007, entitled "Tranceiver System With Reduced Latency Uncertainty" by Neville Carvalho et al. 009,012, which is hereby incorporated by reference. technical field [0003] The present invention relates to reducing delay time uncertainty. Background technique [0004] figure 1 is a block diagram of a system with delay time uncertainty. exist figure 1 In the system 100 includes a receiver 110 , a word aligner (aligner) 120 , user logic 130 , a phase-interleaved first-in-first-out (FIFO) 150 and a transmitter 160 . The receiver and transmitter may be denoted herein as RX and TX, respectively. A combination of a receiver and a transmitter may be referred to herein as a transceiver. In addition to referring to a combination of receiver and transmitter, transceiver may also be used herein to refer to either a receiver or a transmitter. Bec...

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Problems solved by technology

Therefore, there is an uncertainty of one clock cycle (cycle) between the recovered clock and the transmitter parallel clock

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