IEEE1588 synchronous accuracy test device based on networking LXI measurement and control system
A technology of synchronization accuracy and test device, which is applied in time division multiplexing systems, electrical components, multiplexing communications, etc. System working parameters, etc.
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specific Embodiment approach 1
[0015] Specific implementation mode one, see figure 1 This embodiment will be described. The IEEE1588 synchronization accuracy testing device based on the networked measurement and control LXI system described in this embodiment is composed of a computer 1, a network connection device 2, a master clock node 3 and a plurality of slave clock nodes 4, wherein the master clock node 3 and each The slave clock node 4 is connected to the network connection device 2 through an Ethernet cable, the network connection device 2 is connected to the computer 1 through an Ethernet cable, and the CVI interface subsystem is embedded in the computer 1, wherein:
[0016] The CVI interface subsystem is used to read the system configuration file, and obtain the total number of master clock nodes 3 and slave clock nodes 4 in the system; it is also used to apply for system resources according to the total number, and communicate with master clock nodes 3, Each slave clock node 4 establishes a TCP c...
specific Embodiment approach 2
[0037] Specific embodiment 2. In this embodiment, on the basis of the IEEE1588 synchronization accuracy test device based on the networked measurement and control LXI system described in the specific embodiment 1, the slave clock node 4 is also used to obtain clock offset information. The effective bit of the clock offset information is 1; it is also used to judge whether the effective bit of the clock offset information is 1; when the effective bit of the clock offset information is 1, the clock offset information is sent to the CVI interface subsystem, and the The effective bit of the clock offset information is 0, and when the effective bit of the clock offset information is not 1, the slave clock node continues to wait for judgment.
[0038] The workflow of slave clock node 4 in this embodiment: see Figure 5 As shown, after the third step C3, there is also a step C3-1, the first step C3-1: at each synchronization, the effective position of the clock offset information is ...
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