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Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole

A dual damascene process, semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc.

Inactive Publication Date: 2010-03-10
CANON KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it is difficult to transfer the pattern to Cu itself

Method used

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  • Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
  • Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
  • Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole

Examples

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Comparison scheme
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no. 1 example

[0035] will refer to Figure 1A and 1B A first embodiment according to an aspect of the present invention will be described.

[0036] A member 1999 ( Figure 1A ).

[0037] The above-mentioned second insulating film 1002 is produced by embossing a pattern (not shown in the drawings) on the layer after providing a layer on the above-mentioned first insulating film 1001, and the pattern corresponds to the wiring groove 1003 and the first insulating film 1002. A through hole 1004 .

[0038] For example, when contacted with the above-mentioned mold, the material constituting the layer is solidified, thereby producing the second insulating film.

[0039] In the present invention, the layer also includes the case where the material for forming the second insulating film is in the form of a layer on the first insulating film macroscopically, but is in the form of dots microscopically.

[0040] Furthermore, in the present invention, the layer includes the case where the material for ...

no. 2 example

[0103] Second Example: Planarization

[0104] A second embodiment according to another aspect of the present invention is a method of manufacturing a semiconductor device by using the above-mentioned dual damascene process. However, it is characterized by including the step of preparing a member having a first insulating film on a substrate, wherein the first insulating film has been subjected to planarization.

[0105] will refer to Figures 6A to 6E This embodiment will be described.

[0106] exist Figure 6A , reference numeral 1800 denotes an uneven substrate.

[0107] Here, the substrate includes a substrate composed of a multilayer film. The above-mentioned multilayer film includes a conductive layer formed of Cu or the like or an insulating layer formed of SiC or the like.

[0108] A first insulating film 1801 is provided on a substrate 1800, and the first insulating film 1801 has been subjected to a planarization process in order to reduce unevenness.

[0109] Th...

no. 3 example

[0129] The third embodiment: optical printing

[0130] The method for manufacturing the semiconductor device according to the third embodiment of the present invention is performed as follows.

[0131] A member having a first insulating film is prepared on a substrate.

[0132] Furthermore, a model having patterns corresponding to the wiring trenches and the first via holes is prepared.

[0133] An ultraviolet curable resin layer is inserted between the mold and the first insulating film, and the resin layer is irradiated with ultraviolet rays to be cured.

[0134] After curing the resin, the above-mentioned mold and resin are separated from each other. If necessary, the above cured resin is subjected to anisotropic etching (so-called etch-back step).

[0135] In this way, the second insulating film having the aforementioned wiring trench and the aforementioned first via hole can be produced.

[0136] The above-mentioned first insulating film is selectively etched by using...

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Abstract

A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulatingfilm is prepared on a substrate, and a layer is disposed on the above-described first insulating film. A mold having a pattern is imprinted on the above-described layer so as to form a second insulating film having a wiring trench and a first via, the pattern corresponding to the wiring trench and the first via. Thereafter, the above-described first insulating film is etched by using the above-described second insulating film as a mask so as to form a second via, which is connected to the first via, in the first insulating film.

Description

[0001] This application is a divisional application of an invention patent application with the application number 200610164091.8, the application date is December 7, 2006, and the invention title is "Method for Manufacturing Semiconductor Devices Using Dual Damascene Technology and Method for Manufacturing Products with Connecting Holes". technical field [0002] The present invention relates to a method of manufacturing an article having communicating holes. Furthermore, the present invention relates to a method of manufacturing a semiconductor device by using a dual damascene process. Background technique [0003] Generally, Cu has been used as a wiring material of semiconductor devices. However, it is difficult to transfer patterns to Cu itself. Accordingly, attention has been paid to a damascene process, particularly a dual damascene process, in which trenches for wiring or forming electrodes and via holes are simultaneously formed. [0004] Regarding a method of manu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
Inventor 寺崎敦则关淳一田中一郎
Owner CANON KK
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