Lateral DMOS transistor and method of fabricating thereof

A technology of transistors and body regions, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve problems such as the limitation of drain-source impedance

Inactive Publication Date: 2010-05-26
DONGBU HITEK CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] Therefore, when maintaining the level of the breakdown voltage BVd

Method used

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  • Lateral DMOS transistor and method of fabricating thereof
  • Lateral DMOS transistor and method of fabricating thereof
  • Lateral DMOS transistor and method of fabricating thereof

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Embodiment Construction

[0021] Reference will now be made in detail to specific embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0022] figure 2 A cross-sectional view showing an LDMOS transistor according to a preferred embodiment of the present invention is shown. refer to figure 2 , the LDMOS transistor includes: N well 210, formed on the P-type semiconductor substrate 200; LOCOS 230, formed on the surface of the N well 210; drain region 260, formed in the N well 210, on one side of the LOCOS 230; and doped N + Type impurity source region 252, doped with P + Type impurity source contact region 254; and a second gate electrode 256 having a trench shape, formed in the P-type body region 250, which is separated from the drain region 260 by a certain distance, in the LOCOS 230 on the other side of the .

[0023] Source region 252 ...

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PUM

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Abstract

A LDMOS transistor and a method for fabricating the same. A LDMOS transistor may include a P-type body region formed over a N-well. A LDMOS transistor may include a source region and a source contact region formed over a P-type body region. A LDMOS transistor may include a drain region spaced a distance from a P-type body region. A LOCOS may be formed over a surface of a N-well between a P-type body region and a drain region. A LDMOS transistor may include a main gate electrode formed over at least a portion of a LOCOS and a N-well. A LDMOS transistor may include a sub-gate electrode formed between a source region and a source contact region. A method for fabricating a LDMOS transistor is described herein.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2008-0096626 filed on Oct. 1, 2008, the entire contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to semiconductor devices, and more particularly, to LDMOS transistors and methods of manufacturing the same. Background technique [0003] Ideally, as a power semiconductor device, a device that can operate close to the theoretical breakdown voltage of the semiconductor is preferred. [0004] Therefore, in the case of controlling an external system using a high voltage through an integrated circuit, the integrated circuit requires a built-in device for controlling the high voltage, which is provided with a structure having a high breakdown voltage. [0005] That is, in the drain or source of a transistor with a high voltage directly applied thereto, the punch-through voltage between the drain and source and the semiconductor substrate, and the...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/423H01L21/336H01L21/28
CPCH01L29/0878H01L29/66704H01L29/42368H01L29/7825H01L29/7831
Inventor 李相容
Owner DONGBU HITEK CO LTD
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