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Packet relay device

A relay device and technology for receiving packets, applied in digital transmission systems, electrical components, transmission systems, etc., can solve problems such as volume reduction

Inactive Publication Date: 2010-05-26
ALAXALA NETWORKS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, if the operation clock of the packet relay device is simply lowered to save power, the amount of packets that the packet relay device can transmit per unit time may decrease.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0038] (A1) Outline of the structure of the packet relay device as the first embodiment

[0039] (A2) Concrete structure of the bandwidth monitoring section

[0040] (A3) Bandwidth monitoring processing

no. 2 Embodiment

[0042] (B1) Outline of the structure of the packet relay device as the second embodiment

[0043] (B2) The specific structure of the packet sending circuit

[0044] (B3) Bandwidth monitoring processing

[0045] C.Modification

[0046] A. The first embodiment

[0047] (A1) Outline of the structure of the packet relay device as the first embodiment

[0048] figure 1 It is a diagram showing an outline of the configuration of the packet relay device 10 as the first embodiment of the present invention. The packet relay device 10 is a device that connects different networks and relays packets transmitted between these networks.

[0049] Such as figure 1As shown, the packet relay device 10 has: a packet receiving circuit 12, which receives packets from other communication devices; a relay control unit 14, which analyzes the header information of the packets received by the packet receiving circuit 12, and determines the relay purpose ground processing (hereinafter referred to ...

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PUM

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Abstract

The packet relay device includes a clock generation portion adapted to generate a clock signal of prescribed frequency as a standard for operation of the packet relay device; a timer portion adapted to count up a timer value over a first number of clock cycles on the basis of the clock signal; a relay control portion adapted relay received packets while limiting to a prescribed amount of packets the amount of packets forwardable per a predetermined increment of the timer value; and a power control portion adapted to reduce the frequency of the clock signal to 1 / n in order to reduce power consumption by the packet relay device. If the frequency of the clock signal has been reduced to 1 / n by the power control portion, the timer portion counts up the timer value over a number of clock cycles equivalent to 1 / n the aforementioned number of clock cycles.

Description

technical field [0001] The present invention relates to a technique for reducing power consumption of a packet relay device that relays packets. Background technique [0002] Packet relay devices represented by switches and routers are extremely important devices when building a network. In recent years, the processing capability (packet relay capability) of packet relay devices has been significantly improved with the increase in the size of the network and the increase in the amount of packets to be relayed. [0003] In order to increase the processing capability of the packet relay device, it is essential to increase the speed of the operation clock, but in recent years, the amount of power consumed by the packet relay device has increased with the increase in speed of the operation clock. Therefore, the following Patent Document 1 discloses a technology for reducing the operating clock of the packet relay device according to the utilization state of the packet relay dev...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56G06F1/04G06F1/08H04L29/02H04L29/08
CPCH04L47/28H04L47/20H04L47/215
Inventor 石川有一
Owner ALAXALA NETWORKS
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