Serial port caching control method, controller and microcontroller system thereof

A microcontroller and controller technology, applied in the direction of memory address/allocation/relocation, input/output to record carrier, etc., can solve problems affecting the execution efficiency of the microcontroller system, and achieve the effect of increasing efficiency

Active Publication Date: 2011-07-27
SUNPLUS INNOVATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the microcontroller 11 is in a waiting state during the data download, if the amount of data downloaded each time is too large, it will affect the execution efficiency of the microcontroller system 30
Moreover, in the 256-byte data downloaded each time, not necessarily all the data will be read, so there is still room for improvement in the prior art

Method used

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  • Serial port caching control method, controller and microcontroller system thereof
  • Serial port caching control method, controller and microcontroller system thereof
  • Serial port caching control method, controller and microcontroller system thereof

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Embodiment Construction

[0029] The serial interface cache controller, control method and microcontroller system using the controller of the present invention will be described in detail below with reference to the drawings.

[0030] For a general cache controller, its tag address column is only used to record the highest M-bit address, for example, an 8-bit address. Therefore, the amount of data corresponding to each tag address column is 256 bits. If the value of M is increased, although the amount of data corresponding to each tag address row will decrease, correspondingly, the tag address row must be increased so that the stored cache data amount remains the same. The higher the number of tag address columns, the higher the complexity and cost of the cache controller. For example, if the value of M is 8, and the cache controller has 8 tag address columns, an internal cache memory of 2048 bytes is required, and the amount of data downloaded from the external memory each time is 256 bytes. If the ...

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Abstract

The invention provides a serial port caching control method, a controller and a microcontroller system thereof. The serial port caching controller comprises L label address rows, wherein each label address row comprises a block label of an M bit and an effective bit zone label of an N bit; the block label of the M bit is used for recording an address zone of T byte data stored in an internal caching memory, the effective bit zone label of the N bit is used for recording effective bit zones in the address zone, wherein the size of each effective bit zone is T / N byte. The serial port caching controller needs to read T / N byte data from an external memory to the internal caching memory every time without reading the T byte data of the whole address zone. Because the T byte data of the whole address zone can not necessarily be read by a microcontroller, the waiting time of the microcontroller can be shortened so that the executing speed is raised.

Description

technical field [0001] The invention relates to a cache controller of a serial interface, in particular to a cache controller capable of reducing the amount of data read from an external memory to reduce the bandwidth of the serial interface of the cache memory. Background technique [0002] figure 1 It is an architectural diagram of a microcontroller system that generally accesses external memory data in parallel. Such as figure 1 As shown, the microcontroller system 10 includes a microcontroller (Micro-controller) 11 and is connected to an external memory (External memory) 12 . The external memory 12 can be a flash memory (Flash memory) or other forms of memory that can store data. The micro-control system 10 accesses the data of the external memory 12 in parallel, so the micro-control system 10 must be designed with quite a lot of pads, including address buses, data buses, and the like. Therefore, although the micro-control system 10 has a faster access speed, it will...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F3/06
Inventor 徐汉华
Owner SUNPLUS INNOVATION TECH
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