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Reduce instruction conflicts in processors

A technology of processors and instructions, applied in the field of superscalar computers, can solve problems such as waste of computing time and workload, and instruction conflicts

Active Publication Date: 2014-10-22
STMICROELECTRONICS BEIJING R& D
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, it may happen that the selection logic for two different functional units selects the same instruction for execution in the same cycle, that is, at the same time
This situation is known as an instruction conflict and wastes computation time and effort

Method used

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  • Reduce instruction conflicts in processors
  • Reduce instruction conflicts in processors
  • Reduce instruction conflicts in processors

Examples

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Embodiment Construction

[0018] The following discussion is presented to enable any person skilled in the art to make and use the subject matter disclosed herein. The general principles disclosed herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the subject matter disclosed herein. The disclosure is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or discussed herein.

[0019] As an overview, methods and systems formed in accordance with the subject matter disclosed herein can select instructions from an instruction issue queue for execution at multiple functional units while reducing the chance of instruction conflicts where when more than one functional unit attempts to execute an instruction issue When the same instruction is in the queue, the instruction conflict may cause the NOP instruction to be executed. In one embodiment, each fu...

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Abstract

An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Description

technical field [0001] The present invention relates to superscalar computers, and more particularly, the present invention relates to methods and systems that can select instructions from an instruction issue queue for execution at multiple functional units. Background technique [0002] In computer architecture, a superscalar computer, that is, a computer that has multiple processing elements that together can execute more than one instruction per clock cycle, can be used for computationally intensive applications. Typically, a superscalar computer will employ a central processing unit (CPU) that includes multiple execution resources, such as one or more functional units, for executing multiple instructions concurrently. Examples of functional units may include arithmetic logic units, bit shifters, or multipliers. Using multiple functional units to execute multiple instructions concurrently may allow for faster throughput across the CPU than would otherwise be possible wi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
CPCG06F9/3855G06F9/3836G06F9/3856
Inventor 王凯峰孙红霞朱鹏飞吴永强
Owner STMICROELECTRONICS BEIJING R& D